Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-31
2003-08-26
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S750000, C257S761000, C257S722000, C428S624000, C165S080300, C165S185000
Reexamination Certificate
active
06610595
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor Integrated Circuits (IC), and more specifically, to a bump limiting metallurgy (BLM) for input/output of a device.
2. Discussion of Related Art
Input/outputs are used in a device to condition and distribute power, ground, and signals. The I/Os can be wirebonded to a package or board with leads formed from Gold (Au) or Copper (Cu) wire. However, when the number of I/Os reaches about 400 to 1000, bumping often becomes more advantageous than wirebonding.
FIG.
1
(
a
) and FIG.
1
(
b
) show a solder bump
15
with a diameter
1
and a pitch
2
. The solder bump
15
is formed on Ball Limiting Metallurgy (BLM)
14
. BLM is also known as Pad Limiting Metallurgy (PLM) or Under Bump Metallurgy (UBM). The BLM
14
is connected through a via
12
in the passivation layer
13
to an underlying bond pad
11
b
. The passivation layer
13
, comprises one or more layers of materials, such as silicon oxide, silicon nitride, or polyimide, which act as a barrier to moisture, ions, or contaminants. The bond pad
11
b
is a widened portion of a metal line
11
a
in the top metal layer of the device. The line
11
a
is connected to an underlying via
10
that is, in turn, connected to an underlying line
9
. A device typically has 2 to 8 metal layers so a via and a line are alternated vertically until electrical contact is made to the desired part of the IC or the substrate below.
Bumping can significantly improve access to the core area and maximize utilization of the silicon area. FIG.
1
(
a
) and FIG.
1
(
b
) show an areal array
3
of bumps
15
across the entire active area of the chip. The array
3
is substantially periodic and may be face-centered cubic or hexagonal to achieve a higher density of bumps
15
. A bumped device is turned over and packaged as a Flip Chip (FC). A solder bump technology based on Controlled Collapse Chip Connection (C4) may be used for Direct Chip Attach (DCA) to conductive traces on a package or circuit board. The circuit board may be a ceramic substrate, Printed Wiring Board (PWB), flexible circuit, or a silicon substrate. Bumping a device also reduces the resistance and inductance in the I/Os thus significantly improving performance.
A high performance device, such as a microprocessor, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or a System-on-a-Chip (SOC), may have about 600 to 7000 I/Os so the I/Os need to be scaled down to limit die size. Wirebonding may involve a pitch of less than 60 microns using wires with a diameter of less than 25 microns with ball bonds of less than 40 microns. Bumping may involve bumps with a diameter of about 45 to 90 microns and a pitch of about 125 to 300 microns.
Power management and thermal management become very critical when wire leads or bumps are scaled down. I/Os may fail if junction temperature exceeds 100 to 125 degrees C or current density exceeds 150 to 425 milliamperes per I/O. Electromigration or thermomigration can increase resistance by over 2 orders of magnitude before finally resulting in an open circuit. Elevated temperatures can also cause inter-diffusion of metals. The resultant intermetallic alloys are brittle and may be susceptible to stress cracking. A mismatch in the Coefficient of Thermal Expansion (CTE) can result in large shear stresses on a wire lead or bump. For example, solder has a CTE of about 30 ppm/degree C compared with about 7 ppm/degree C for a ceramic substrate and about 5 ppm/degree C for a Silicon substrate. A wire lead or bump may fail from thermal shock if the thermal ramp rate exceeds about 15 to 20 degrees C/minute. Thermal cycling at lower thermal ramp rates may also cause a wire lead or bump to crack due to fatigue induced by elastic deformation or creep deformation.
Thus, the failure of I/Os, especially the power I/Os, due to high currents and high temperatures is a major concern.
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patent: 5442239 (1995-08-01), DiGiacomo et al.
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patent: 6162652 (2000-12-01), Dass et al.
patent: 6312830 (2001-11-01), Li et al.
patent: 2000 091369 (2000-03-01), None
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International Search Report PCT/US 01/18666.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Tran Mai-Huong
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