Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-01-03
2003-12-23
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S696000, C257S698000, C257S666000, C257S673000, C257S712000, C257S713000, C257S774000, C257S737000, C257S738000, C257S784000, C257S786000, C257S717000, C257S720000, C257S707000, C257S796000
Reexamination Certificate
active
06667546
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a BGA (ball grid array) semiconductor package with improvements in electrical and heat dissipating efficiency.
BACKGROUND OF THE INVENTION
A BGA (ball grid array) semiconductor package, a main stream of package products, is characterized of implanting a plurality of array-arranged solder balls on a bottom surface of a substrate. The solder balls acting as I/O (input/output) connections are densely arranged in response to high density of electronic components and electronic circuits incorporated with a semiconductor chip, so that the BGA semiconductor package can be applied to electronic products in favor of desirable advantages such as high electrical performance and processing speed. The solder balls deposited on the substrate are used to electrically connect the semiconductor chip to external devices e.g. printed circuit board (PCB), allowing the semiconductor package to operate with multiple functions of grounding, powering, signaling. Therefore, the substrate is formed with corresponding mechanisms that are electrically connected to the differently functioned solder balls, in an effort to achieve desirable performances of internal elements in operation of the semiconductor package.
Accordingly, U.S. Pat. Nos. 5,581,122, 5,545,923 and 5,726,860 disclose the configuration of forming a ground ring, a power ring and signal fingers on a substrate. As shown in
FIGS. 5 and 6
of a semiconductor structure
1
, on an upper surface
100
of a substrate
10
there are provided a ground ring
11
, a power ring
12
and a plurality of signal fingers
13
at positions outside a chip attach region
101
. After a chip
14
is mounted on the chip attach region
101
, a wire bonding process is performed, and a plurality of ground wires
15
, power wires
16
and signal wires
17
are formed for electrically connecting bond pads
140
disposed on the chip
14
to the ground ring
11
, the power ring
12
and the signal fingers
13
, respectively. Then, in subsequent processes, a plurality of solder balls
18
are implanted on a lower surface
102
of the substrate
10
, and electrically connected to the ground ring
11
, the power ring
12
and the signal fingers
13
by conductive traces
19
, respectively. This therefore makes the semiconductor structure
1
capable of being electrically connected to an external device (not shown) for chip operation. It should be understood that, the drawings are made in simplicity with illustration of only associated elements relating to the invention; in practice, a semiconductor structure is much more complex in element layout and arrangement.
However, the foregoing semiconductor structure is endowed with multiple drawbacks. First, the ground ring and the power ring significantly occupy surface area of the substrate; this undesirably restricts trace routability on the substrate, and also makes the substrate not able to be further reduced in dimensions, which is not in favor of profile miniaturization. Moreover, in order to reduce signal interference, a decoupling pad (not shown) is usually incorporated in the conventional semiconductor structure, and may further limit the trace routability on the substrate. In addition, the need of making many ground wires, power wires and signal wires greatly increases the complexity of fabricating processes. As shown in
FIG. 5
, these wires are arranged with multiple layers of wire loops, and different layers of wire loops need to be precisely controlled in elevation for allowing the wire loop layers to be properly spaced apart from each other. This undoubtedly increases the difficulty in fabrication; for example, during injection of a molding resin used in a molding process, impact of the mold flow may easily lead to adjacent wire loops coming into contact with each other and results in short circuit, thereby making quality and yield of products seriously damaged.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a BGA semiconductor package with no provision of a power ring and a ground ring.
Another objective of the invention is to provide a BGA semiconductor package without forming power wires and ground wires.
Still another objective of the invention is to provide a BGA semiconductor package, which does not increase the restriction on trace routability of a substrate.
A further objective of the invention is to provide a BGA semiconductor package, so as to increase heat dissipating efficiency and provide an EMI (electric Magnet Interference) shielding effect for the semiconductor package.
In accordance with the above and other objectives, the present invention proposes a BGA semiconductor package, comprising: a substrate having a first surface and an opposing second surface, the first surface being formed with a chip attach region and a plurality of signal fingers surrounding the chip attach region, the first surface further being defined with a power attach region and a ground attach region in proximity to two sides of the substrate at positions outside the signal fingers; at least a chip having an active surface and an opposing non-active surface, the active surface being disposed with a plurality of signal pads, power pads and ground pads at peripheral area thereof, wherein the power pads are consolidated to form a power plane on the active surface of the chip and electrically connected to the power plane, and the ground pads are consolidated to form a ground plane on the active surface of the chip and electrically connected to the ground plane; the non-active surface of the chip being attached to the chip attach region of the substrate in a manner that, the power plane and the ground plane of the chip face toward the power attach region and the ground attach region on the substrate, respectively; a plurality of bonding wires for electrically connecting the signal pads of the chip to the signal fingers on the first surface of the substrate; a power plate with two ends thereof being respectively attached to the power plane of the chip and the power attach region of the substrate in a manner free of interference with layout of the bonding wires; a ground plate with two ends thereof being respectively attached to the ground plane of the chip and the ground attach region of the substrate in a manner free of interference with layout of the bonding wires; an encapsulant formed on the first surface of the substrate, for encapsulating the chip, the bonding wires, the power plate and the ground plate.
A plurality of signal ball pads, power ball pads and ground ball pads are disposed at predetermined positions on the second surface of the substrate. A plurality of vias penetrating the substrate are used to electrically connect the signal ball pads to the signal fingers on the first surface of the substrate, and electrically connect the power ball pads and the ground ball pads to the power attach region and the ground attach region on the first surface of the substrate, respectively. And, the solder balls are implanted at the signal ball pads, the power ball pads and the ground ball pads on the second surface of the substrate. Moreover, the power pads and the ground pads on the active surface of the chip are re-distributed to form a plurality of traces, which traces consolidate and electrically connect the power pads and the ground pads to the power plane and the ground plane, respectively.
The metal-made power plate is composed of a protruding portion, a flat portion and a supporting portion, wherein the protruding portion is attached to the power plane of the chip, and the supporting portion is attached to the power attach region of the substrate, allowing the flat portion to be elevated in position above the chip by the protruding portion and the supporting portion in a manner free of interference with the bonding wires. Similarly, the metal-made ground plate includes a protruding portion, a flat portion and a supporting portion. The protruding portion of the ground plate is atta
Huang Chien-Ping
Huang Chih-Ming
Ko Eric
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
Williams Alexander O.
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