Ball grid array package with conductive leads

Details Ball grid array package with conductive leads Ball grid array package with conductive leads

1999-09-10

2001-02-06

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With provision for cooling the housing or its contents

C257S706000, C257S711000, C257S712000, C257S717000, C257S718000, C257S780000

Reexamination Certificate

active

06184580

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a packaging structure for a silicon chip. More particularly, the present invention relates to a ball grid array package with conductive leads.
2. Description of Related Art
In the manufacturing of integrated circuits, ultimate size of the package is an important issue. As the level of integration and functions of integrated circuits increase, the number of conductive leads required for connections with external circuitry are also increased. Furthermore, as the operating speed of silicon chip continue to increase, the amount of heat generated by the chip and electrical interference caused by external electromagnetic fields during operation can no longer be ignored. An increase in the level of integration leads to an increase in conductive lead-count under the same chip volume. However, when the number of conductive leads increases, distance between neighboring leads have to become smaller, thereby increasing the level of difficulties in packaging a silicon chip. Consequently, a packaging structure has been developed from the peripheral-arranged leadframe structure to a high-density area array structure. A typical high-density area array structure is the ball grid array (BGA) structure. To further reduce the footprint requirement of a ball grid array assembly and increase the number of conductive leads available, a ball grid array structure having additional conductive leads around the periphery of the package has been developed as well. Nonetheless, the thermal efficiency and the electromagnetic interference problems need to be carefully considered in the design of a high-density area array package.
FIG. 1
is a schematic, cross-sectional view showing a typical ball grid array package having a heat sink and conductive leads. As shown in
FIG. 1
, a silicon chip
10
is mounted on a surface of substrate
12
. A heat sink
16
is directly mounted on top of the silicon chip
10
so that heat generated by the chip
10
during operation can be conducted away rapidly. The conductive leads
14
are mounted on the substrate
12
and surrounding the chip
10
. A back surface of the chip
10
is thermally coupled to some solder balls
19
′ on another surface of the substrate
12
so that heat can also be conducted away, In general, the substrate
12
is laminated with each layer includes some conductive traces. Different trace layers are electrically connected by vias. Furthermore, the trace layer located on the surface of the substrate
12
possesses contact points
13
for electrical connections with the silicon chip
10
. A plurality of solder balls
19
is placed on the other side of the substrate
12
for electrical connections with a printed circuit board. The silicon chip
10
is electrically connected to the contact points
13
and the conductive leads
14
through electrical wires
15
and
17
, respectively. Hence, electrical signals within the chip
10
are able to pass onto the substrate
12
and the conductive leads
14
. A molding compound
18
encloses the silicon chip
10
and the wires
15
and
17
. The molding compound
18
also fills the space between the heat sink
16
, the chip
10
, the conductive leads
14
, and the substrate
12
while exposing a surface of the heat sink
16
. Thus, the chip
10
, the substrate
12
, and inner portion of the leads
14
are protected while heat can be conducted away through the exposed surface of the heat sink
16
.
The aforementioned package structure not only has an area array of solder balls, but also contains a plurality of conductive leads
14
coming out from the edge of the package. Hence, the package can have a relatively small footprint while the number of connections is maintained. However, the heat sink
16
is a structure that floats above the silicon chip
10
, and electric charges may accumulate. Thereby, a parasitic capacitance may be generated leading to the distortion of signals from the chip
10
.
SUMMARY OF THE INVENTION
Accordingly, a first object of the present invention is to provide a ball grid array package with conductive leads, which improves the thermal efficiency of the package.
A second object of the invention is to provide a ball grid array package with conductive leads, which prevents interference of external electromagnetic fields.
A third object of the invention is to provide a ball grid array package with conductive leads, which eliminates a parasitic capacitor between the chip, or the wires, and the heat sink. Hence, the performance of the package can be improved.
A fourth object of the invention is to provide a ball grid array package with conductive leads, which increases the reliability and the yield of a surface mounting operation.
A fifth object of the invention is to provide a ball grid array package with conductive leads having cavity down packaging structure, which decreases the overall thickness of the package.
To achieve these and other advantages and in accordance with the purpose of the resent invention, as embodied and broadly described herein, the present invention provides a ball grid array package with conductive leads. The package includes a silicon chip, a pair of heat sinks, a plurality of conductive leads, a substrate, a plurality of solder balls, and a molding compound. The silicon chip is supported by a carrier. The carrier is an assembly that includes a first heat sink having an exposed surface and a bottom surface, the conductive leads, and the substrate. The conductive leads are sandwiched between the bottom surface of the first heat sink and a surface of the substrate. The conductive leads and the substrate are positioned below the first heat sink and surrounded a die-attach region on the bottom surface of the first heat sink. A back surface of the silicon chip is attached to the die-attach region on the bottom surface of the first heat sink. Since the conductive leads are ultimately connected to a printed circuit board, some of the heat generated by the chip can be conducted away through the conductive leads. In addition, since the first heat sink can be grounded through a lead connection to the printed circuit board, most of the external electromagnetic fields can be screened. A plurality of solder balls is placed on another surface of the substrate. The solder balls are electrically connected to the chip by means of trace lines within the substrate and bonding wires. Since an active surface of the chip and the solder balls are on the same side, this is a cavity down package. Electrical connections between the solder balls and the chip are achieved by bonding wires which are accommodated in spaces between the substrate, and the solder balls. Hence, no additional space for accommodating the bonding wires is required. The molding compound encloses spaces between the chip and the conductive leads, the substrate, and the solder balls.
To increase the heat dissipation capacity of the package, a second heat sink can be mounted on the active surface of the silicon chip. The second heat sink only covers a portion of the active surface and exposes a bonding pads region on the active surface. A molding compound then fills the space between a rugged surface of the second heat sink, the chip, the conductive leads, and the substrate. An exposed surface of the second heat sink is on the same horizontal level as outer portion of the conductive leads. Thus, the exposed surface is in contact with the printed circuit board on which the package is mounted. The rugged surface is between the exposed surface and a mounting surface so that the second heat sink is solidly mounted when the space is filled by the molding compound. In addition to high heat dissipation capacity, the second heat sink, the first heat sink, and the conductive leads together form an ideal shield as well for external electromagnetic radiation. Hence, the silicon chip is able to operate more reliably at a high voltage and high frequency.
It is to be understood that both the foregoing general description and the following detailed

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