Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2005-08-23
2005-08-23
Thompson, Craig A. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S108000, C438S127000, C257S778000, C257S712000, C264S272170
Reexamination Certificate
active
06933176
ABSTRACT:
A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a heat spreader, the semiconductor die and the substrate. The heat spreader is fixed to the at least one of the first surface of the substrate and the semiconductor die such that he at least one collapsible spacer is disposed therebetween. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.
REFERENCES:
patent: 5172213 (1992-12-01), Zimmerman
patent: 5311060 (1994-05-01), Rostoker et al.
patent: 5339216 (1994-08-01), Lin et al.
patent: 5444025 (1995-08-01), Sono et al.
patent: 5493153 (1996-02-01), Arikawa et al.
patent: 5610442 (1997-03-01), Schneider et al.
patent: 5639694 (1997-06-01), Diffenderfer et al.
patent: 5650663 (1997-07-01), Parthasarathi
patent: 5679978 (1997-10-01), Kawahara et al.
patent: 5705851 (1998-01-01), Mostafazadeh et al.
patent: 5736785 (1998-04-01), Chiang et al.
patent: 5773362 (1998-06-01), Tonti et al.
patent: 5877552 (1999-03-01), Chiang
patent: 5977626 (1999-11-01), Wang et al.
patent: 5986885 (1999-11-01), Wyland
patent: 6037658 (2000-03-01), Brodsky et al.
patent: 6236568 (2001-05-01), Lai et al.
patent: 6251706 (2001-06-01), Paniccia
patent: 6323066 (2001-11-01), Lai et al.
patent: 6414385 (2002-07-01), Huang et al.
patent: 6462405 (2002-10-01), Lai et al.
patent: 6525421 (2003-02-01), Chia et al.
patent: 6631078 (2003-10-01), Alcoe et al.
patent: 6656770 (2003-12-01), Atwood et al.
patent: 2001/0015492 (2001-08-01), Akram et al.
patent: 2002/0005578 (2002-01-01), Kodama et al.
patent: 2002/0006718 (2002-01-01), Distefano
patent: 2002/0180035 (2002-12-01), Huang et al.
patent: 2002/0185734 (2002-12-01), Zhao et al.
patent: 2003/0034569 (2003-02-01), Caletka et al.
patent: 100 15 962 (2001-10-01), None
U.S. Appl. No. 10/643,961, filed Aug. 20, 2003, Chun Ho Fan et al., “Improved Ball Grid Array Package and Process for Manufacturing Same”.
U.S. Appl. No. 10/323,657, filed Dec. 20, 2002, Chun Ho Fan et al., “Process for Manufacturing Ball Grid Array Package”.
U.S. Appl. No. 10/372,421, filed Feb. 24, 2003, Joseph Andrew Martin et al., “Improved Ball Grid Array Package”.
U.S. Appl. No. 10/197,832, filed Jul. 19, 2002, Joseph Andrew Martin et al., “Improved Ball Grid Array Package”.
Fan Chun Ho
Kirloskar Mohan
McLellan Neil
Asat Ltd.
Berezny Nema
Keating & Bennett LLP
Thompson Craig A.
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