Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2005-07-26
2005-07-26
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S691000, C257S698000, C257S773000, C257S784000
Reexamination Certificate
active
06921981
ABSTRACT:
A BGA package comprises a chip with an array pad design disposed on the top surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof. The bonding pads of the chip are positioned in three rows, an inner row, a middle row, and an outer row along the sides of the chip. All of the power supply pads and ground pads are adjacent to one another and designed in the outer row of the bonding pads, and the I/O pads are designed in the outer row, the middle row and the inner row of the bonding pads. The outer row, middle row, and the inner row of the bonding pads are electrically connected to the substrate through three tiers of bonding wires with different loop height, respectively.
REFERENCES:
patent: 5528083 (1996-06-01), Malladi et al.
patent: 6034427 (2000-03-01), Lan et al.
patent: 6037669 (2000-03-01), Shu et al.
patent: 6291898 (2001-09-01), Yeh et al.
patent: 10074786 (1998-03-01), None
patent: 2003197748 (2003-07-01), None
Advanced Semiconductor Engineering Inc.
Nadav Ori
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