Ball grid array package

Details Ball grid array package Ball grid array package

2003-02-24

2004-11-16

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S122000, C438S126000, C438S127000

Reexamination Certificate

active

06818472

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to integrated circuit packaging, and in particular to an improved ball grid array package with improved thermal characteristics.
BACKGROUND OF THE INVENTION
High performance integrated circuit (IC) packages are well known in the art. Improvements in IC packages are driven by industry demands for increased thermal and electrical performance, decreased size and cost of manufacture.
In general, array packaging such as Plastic Ball Grid Array (PBGA) packages provide a high density of interconnects relative to the surface area of the package. However typical PBGA packages include a convoluted signal path, giving rise to high impedance and an inefficient thermal path which results in low thermal dissipation performance. With increasing package density, the spreading of heat generated by the device is increasingly important.
Reference is made to
FIG. 1
which shows an elevation view of a portion of a conventional fine pitch BGA (fpBGA) package indicated generally by the numeral
20
. The fpBGA package
20
includes a substrate
22
and a semiconductor die
24
attached to the substrate
22
by a die adhesive. Gold wire bonds electrically connect the die
24
to metal traces on the substrate
22
. The wire bonds and die
24
are encapsulated in a molding compound
26
. Solder balls
28
are disposed on the bottom surface of the substrate
22
for signal transfer. Because of the absence of a thermal path away from the semiconductor die, thermal dissipation in this package is very poor.
One method of improving heat dissipation is the addition of thermal vias in the substrate. The thermal vias connect the die
24
to some of the solder balls
28
for heat dissipation. The thermal vias are small and heat dissipation in high density packages is still poor.
Variations to conventional BGA packages have been proposed for the purpose of increasing thermal and electrical performance.
FIG. 2
shows an elevation view of a portion of a fpBGA package of the prior art with a heat sink
30
. The heat sink
30
is comprised of a metal plate added to the upper portion of the package
20
for dissipating heat from the package
20
. This package still suffers disadvantages, however, as heat must be dissipated from the silicon die
24
, first through the molding compound
26
and then through the heat sink
30
. Thus, heat dissipation away from the silicon die
24
in high density packages is still poor.
Another example of a variation to conventional BGA packages is described in U.S. Pat. No. 5,977,626, issued Nov. 2, 1999, the contents of which are incorporated herein by reference. The '626 patent discloses a PBGA package having a metal heat spreader in contact with an upper surface of the semiconductor die and ground pads on the substrate. The heat spreader is added to dissipate heat from the semiconductor die to the surrounding environment. These packages also suffer disadvantages, however. One particular disadvantage is that the heat spreader and semiconductor die have significantly different thermo-mechanical properties causing induced stress on the semiconductor die during thermal cycling.
It is therefore an object of an aspect of the present invention to provide a BGA package with enhanced thermal properties.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided an integrated circuit package including a substrate having opposing first and second surfaces. The substrate has conductive traces disposed therein. A semiconductor die is mounted on the first surface of the substrate and a silicon heat sink is disposed on a portion of the semiconductor die. A plurality of wire bonds connect the semiconductor die to the conductive traces of the substrate and an overmold material covers the first surface of the substrate and a remainder of the semiconductor die. A ball grid array is disposed on the second surface of the substrate. Bumps of the ball grid array are in electrical connection with the conductive traces.
According to another aspect of the present invention, there is provided a process for fabricating an integrated circuit. The process includes: mounting a semiconductor die to a first surface of a substrate; wire bonding the semiconductor die to conductive traces of the substrate; mounting a silicon heat sink on a portion of the semiconductor die; covering the substrate and a remainder of the semiconductor die with an overmold material; and forming a ball grid array on a second surface of the substrate. The first surface opposes the second surface. Bumps of the ball grid array are electrically connected to the conductive traces.
According to yet another aspect of the present invention, there is provided a process for fabricating an integrated circuit. The process includes: mounting a semiconductor die to a first surface of a substrate; wire bonding the semiconductor die to conductive traces of the substrate; mounting a collapsible structure on a portion of the semiconductor die; mounting a silicon heat sink on the collapsible structure; covering the substrate and a remainder of the semiconductor die with an overmold material; and forming a ball grid array on a second surface of the substrate. The first surface opposes the second surface. Bumps of the ball grid array are electrically connected to the conductive traces.
Advantageously, the silicon heat sink has substantially the same thermo-mechanical properties as the semiconductor die. Thus the coefficient of thermal expansion (CTE) and the elastic modulus of the silicon heat sink are substantially identical to the CTE and elastic modulus, respectively, of the semiconductor die. Also, blank silicon rejects can be used from production, thereby providing an inexpensive heat sink. In a further advantage, the silicon heat sink is mounted on the semiconductor die by a compliant adhesive or by a collapsible structure to inhibit induced stress on the die during molding and to inhibit cracking or damaging the semiconductor die. This structure permits a lack of mold flash on top of the exposed silicon heat sink.
In one aspect, the present invention provides a silicon heat sink mounted on the semiconductor die and having a surface exposed through the molding compound. Thus, a direct thermal path is provided from the semiconductor die to the environment.


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U.S. patent application Ser. No. 10/643,961, Chun Ho Fan et al., “Improved Ball Grid Array Package and Process for Manufacturing Same”, filing date: Aug. 20, 2003.
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U.S. patent application Ser. No. 10/647,696, Mohan Kirlos

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