Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-12-18
2003-11-04
Cuneo, Kamand (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C438S108000
Reexamination Certificate
active
06642626
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor or integrated circuit (IC) package and manufacturing method thereof, and more particularly, to a ball grid array package and manufacturing method thereof for providing an IC package in which leads comprising spherical conductive balls are changed into an hourglass type features.
2. Description of the Related Art
Generally, a ball grid array for an IC package uses conductive balls, such as solder balls and the like, which are arranged on a back surface of a substrate, to provide external leads. As a result, ball grid array packages provide a reduction in IC size, and further reduces the occurrence of lead deformation, unlike QFP (Quad Flat Package) packages.
FIG. 1A
illustrates a cross-sectional view of a ball grid array package according to a first embodiment of a conventional IC package, and
FIG. 1B
illustrates a cross-sectional view of a ball grid array package according to a second embodiment of a conventional IC package.
Generally, ball grid array IC packages having the above-mentioned advantages are divided into two types, a vessel type having conductive balls
114
resembling a ship feature as shown in FIG.
1
A and an hourglass type having an hourglass shaped conductive balls
115
as shown in
FIG. 1B
, in accordance with conventional packages utilizing conductive balls
114
,
115
mounted on a substrate
100
.
A ball grid array package manufactured as either a vessel or hourglass type undergoes a reliance test against heat at a temperature of 200 to 250° C.
During the reliance test against heat at these temperatures, the conductive balls
114
of the vessel type ball grid package are metamorphosed from a spherical type into an elliptic type as shown in FIG.
1
A. Stresses are generated from the interfaces among the conductive balls
114
, a print circuit board (PCB, hereinafter called substrate)
100
in contact with the conductive balls
114
, and a semiconductor chip
110
having a plurality of chip pads
112
, which may result in formation of cracks in one or more of the contacting members.
In order to overcome the manufacturing problems of vessel type packages, an hourglass type ball grid array package having an excellent joint reliance for a solder joint and an excellent thermal reliance has been proposed. Unfortunately, the hourglass type package needs an additional process of pulling up a semiconductor chip in vacuum, which requires using additional equipment so as to metamorphose a conductive ball into an hourglass type cylinder.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a ball grid array IC package and manufacturing method thereof that substantially obviates one or more of the problems resulting from the limitations and disadvantages of the related art.
One object of the present invention is to provide a ball grid array package allowing metamorphosis of a conductive ball into an hourglass feature with ease by maintaining a uniform interval between a semiconductor chip and a substrate.
Another object of the present invention is to provide a method of manufacturing a ball grid array package allowing the metamorphosis of a conductive ball into an hourglass feature with ease by utilizing a member that provides a uniform interval between a semiconductor chip and a substrate.
Additional features and advantages of the invention will be set forth in the following detailed description, and in part will be apparent from the description, or may be learned by practice of the invention as herein disclosed. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, ball grid array IC packages according to the present invention include a semiconductor chip having a plurality of chip pads, a substrate having ball lands, hourglass type conductive balls electrically connected to the chip pads and landed at the ball lands, respectively, and an interval maintaining member maintaining a uniform interval between the semiconductor chip and substrate.
In another embodiment, a method of manufacturing ball grid array IC packages according to the present invention includes the steps of providing a semiconductor chip having a plurality of chip pads, attaching spherical conductive balls and an expansive interval maintaining member on the chip pads, mounting the conductive balls on the ball lands, and expanding a volume of the interval maintaining member by carrying out thermal treatment on the resultant so as to change the spherical conductive balls into shapes including hourglass features.
In a further embodiment, a method of manufacturing ball grid array IC packages according to the present invention includes the steps of providing a semiconductor chip having a plurality of chip pads, forming spherical conductive balls on the chip pads, forming ball lands and an expansive interval maintaining member on a substrate, mounting the conductive balls on the ball lands, and expanding a volume of the interval maintaining member by carrying out thermal treatment on the resultant structure so as to change the spherical conductive balls into shapes having hourglass features.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as described and as claimed herein.
REFERENCES:
patent: 5284796 (1994-02-01), Nakanishi et al.
patent: 6075710 (2000-06-01), Lau
patent: 6153938 (2000-11-01), Kanda et al.
patent: 6184062 (2001-02-01), Brofman et al.
patent: 6559527 (2003-05-01), Brofman et al.
patent: 3-30349 (1999-02-01), None
patent: 003979 (2000-01-01), None
patent: 150697 (2000-05-01), None
patent: 164632 (2000-06-01), None
Cuneo Kamand
Geyer Scott B.
Hynix / Semiconductor Inc.
Ladas & Parry
LandOfFree
Ball grid array IC package and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ball grid array IC package and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ball grid array IC package and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3149637