Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1993-03-19
2001-07-17
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S786000, C257S773000
Reexamination Certificate
active
06262477
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to an electronic package for housing one or more semiconductor devices. More particularly, the invention relates to a surface mount electronic package having a metallic substrate.
BACKGROUND OF THE INVENTION
Microelectronic devices are typically manufactured from a semiconductor material such as silicon, germanium or gallium/arsenide. The semiconductor material is fashioned into a die, a generally rectangular structure having circuitry formed on one surface. Along the periphery of that surface are input/output pads to facilitate electrical interconnection to external components.
The semiconductor device is brittle and requires protection from moisture and mechanical damage. This protection is provided by an electronic package. The electronic package further contains an electrically conductive means to transport electrical signals between the semiconductor device and external circuitry.
One package design which minimizes space requirements and provides a high density of interconnections between the electronic device and external circuitry is the pin grid array package. One pin grid array package has a multi-layer ceramic substrate with conductive circuitry disposed between the layers. The circuitry terminates at conductive pads to which terminal pins are brazed. U.S. Pat. No. 4,821,151 to Pryor et al illustrates a ceramic pin grid array package.
Molded plastic pin grid array packages are disclosed in U.S. Pat. No. 4,816,426 to Bridges et al. A circuit tape has terminal pins electrically interconnected to circuit traces formed on the tape. The assembly is partially encapsulated within a polymer resin.
Metal pin grid array packages are disclosed in U.S. Pat. No. 5,098,864 to Mahulikar. An array of holes is formed through a metallic substrate. Terminal pins pass through the substrate and are electrically isolated from it by a polymer resin. When the metallic substrate is aluminum based, further electrical isolation is by an anodization layer on the surfaces of the substrate.
Pin grid array packages are electrically interconnected to a printed circuit board by insertion of the terminal pins through a matching array of holes formed in a printed circuit board. The holes in the printed circuit board are metallized and electrical interconnection is made within the through holes of the printed circuit board.
Another type of package having a high density of interconnections is a surface mount package. In a surface mount package, the printed circuit board does not require an array of holes. The leads of the package are soldered to bond pads on the printed circuit board. Typically, the leads are either bent under the package in a J-shape or are bent in a gull wing shape and soldered to interconnect pads aligned with the perimeter of the package. This package is disclosed in U.S. Pat. No. 4,706,811 to Jung et al and U.S. Pat. No. 5,065,281 to Hernandez et al. The solder to join the electronic package to the printed circuit board is screened onto the bond pads and may contain fillers such as plated copper spheres to space the package from the board as disclosed in U.S. Pat. No. 4,771,159 to O'Leary.
An advantage of a surface mount package is reduced space requirement on a printed circuit board compared to packages with leads extending from the package body. The interconnection between the surface mount package and a printed circuit board is solder pads located on the surface of the board rather than holes drilled through the board. The number of leads in a typical leaded surface mount package is, however, limited by the peripheral area of the surface mount package.
A limitation with a pin grid array package is the array of holes formed in the printed circuit board must be aligned with the array of terminal pins extending from the package base.
Preferred packages are land grid array packages (electrical interconnection is through metallized pads on the package base) and ball grid array packages (electrical interconnection is through solder bumps formed on the base of the package). The ball grid array package does not require terminal pins and has direct solder bonds between metallized pads on a ceramic base and matching pads on a printed circuit board. Ceramic bases are a relatively poor thermal conductor as are epoxy based laminated printed circuit board bases. Metallic bases would provide an improved land grid array package. However, a means to prevent the solder joints from electrically shorting to the metallic substrate is required. Also, a means to transmit electrical signals from a printed circuit board to an encased electronic device is required.
Applicants have developed a ball grid array package having a metallic substrate which solves these problems.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a ball grid array electronic package having a metallic base. It is the feature of the invention that the metallic base contains a plurality of electrically conductive vias which, in most embodiments, are electrically isolated from the base. One end of the vias is electrically connected to external circuitry while the other end is electrically connected to an integrated circuit device.
Among the advantages of the present invention are the package does not require through holes formed in a system printed circuit board. The package has a finer pitch than a pin grid array package. The ball grid array package requires less peripheral space than a peripherally leaded electronic package. The package has lower lead to lead mutual inductance than leaded packages or leaded surface mount packages as well as lower lead self inductance. The metallic substrate provides enhanced thermal dissipation.
In accordance with the invention, there is provided an electronic package. The electronic package has a metallic base which contains interior and exterior surfaces. A plurality of electrically conductive vias extend through the metallic base with one end terminating approximately at the exterior surface. A first electrically conductive means is bonded to each of the electrically conductive vias adjacent the exterior surface. A second electrically conductive means interconnects the electrically conductive vias to an electronic device mounted on the metallic base. A cover is bonded to the metallic base with the electronic device disposed therebetween.
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patent: 5241133 (19
Braden Jeffrey S.
Hoffman Paul R.
Mahulikar Deepak
Advanced Interconnect Technologies
Clark Sheila V.
Rosenblatt Gregory S.
Wiggin & Dana
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