Ball grid array by partitioned lamination process

Metal fusion bonding – Process – Preplacing solid filler

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22818022, 228 14, B23K 3102

Patent

active

057354529

ABSTRACT:
A method for forming a ball grid array to provide a chip carrier with I/O capabilities is described. The method includes combining three distinct steps into one: partitioning a solder sheet into identical solder pieces using a mask provided with openings that match the footprint of the chip carrier; reflowing the solder pieces into solder balls; and joining the balls to the I/O pads of the chip carrier. By combining these three steps into one, a high throughput, high volume, defect free and contamination free operation for forming I/O connections thus results.

REFERENCES:
patent: 4412642 (1983-11-01), Fisher, Jr.
patent: 5024372 (1991-06-01), Altman et al.
patent: 5241134 (1993-08-01), Yoo
patent: 5573170 (1996-11-01), Sasaki et al.

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