Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2007-04-17
2010-02-09
Stiglic, Ryan M (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S104000, C710S300000
Reexamination Certificate
active
07660925
ABSTRACT:
Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.
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Larson Chad J.
Mata, Jr. Ricardo
Perez Michael A.
Vongvibool Steven
Gerhardt Diana R.
International Business Machines - Corporation
Stiglic Ryan M
Walder, Jr. Stephen J.
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