Balancing logic resource usage in a programmable integrated...

Details Balancing logic resource usage in a programmable integrated... Balancing logic resource usage in a programmable integrated...

2007-05-24

2009-12-22

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S002000

Reexamination Certificate

active

07636907

ABSTRACT:
A computer-implemented method of balancing logic resource usage in a circuit design for a programmable logic device (PLD) can include determining that an assignment of elements of the circuit design to a first type of logic resource of the PLD is unbalanced compared to an assignment of elements of the circuit design to an alternate type of logic resource of the PLD. An Integer Linear Programming (ILP) formulation specifying a balanced assignment of elements to the first and alternate types of logic resources can be generated. A solution for the ILP formulation can be obtained. Selected elements of the circuit design can be re-mapped from the first type of logic resource to the alternate type of logic resource according to the solution of the ILP formulation and the circuit design specifying the re-mapped elements can be output.

REFERENCES:
patent: 6871336 (2005-03-01), Anderson
patent: 2007/0150846 (2007-06-01), Furnish et al.
patent: 2007/0220522 (2007-09-01), Coene et al.
patent: 2008/0021679 (2008-01-01), Bleiweiss et al.
patent: 2008/0216038 (2008-09-01), Bose
Soheil Ghiasi et al.; “A Unified Theory of Timing Budget Management”; Copyright 2004 IEEE; pp. 653-659.

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