Balanced clock placement for integrated circuits containing...

Details Balanced clock placement for integrated circuits containing... Balanced clock placement for integrated circuits containing...

2001-02-15

2002-11-12

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06480994

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to design tools for integrated circuits. More specifically, but without limitation thereto, the present invention relates to a method for placing clock buffers within an integrated circuit containing megacells to minimize clock skew.
Integrated circuits typically include blocks or partitions of multiple circuit elements such as flip-flops, cores, building block circuits called hard macros, “hardmacs”, or megacells. Some circuit elements are generally synchronized by a common clock signal from a clock buffer located within the integrated circuit chip. Using current methods for balanced clock placement, the ideal clock buffer placement may overlap with a megacell. In that case, the clock buffer is simply moved in either the vertical direction or the horizontal direction until an available space is found. This approach may lead to placement of the clock buffer at a large distance from the ideal location, resulting in a large clock skew.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the problems above as well as other problems by providing a balanced clock placement method for each clock buffer in an integrated circuit having megacells that minimizes clock skew.
In one embodiment, the present invention may be characterized as a method of clock buffer placement for minimizing clock skew in an integrated circuit having megacells that includes the steps of (a) finding an ideal location for a clock buffer on an integrated circuit that minimizes clock skew, (b) checking whether the ideal clock buffer location overlaps a megacell, and (c) finding a location for the clock buffer that is closest to the ideal clock buffer location and that does not overlap a megacell.
In another embodiment, the present invention may be characterized as a computer program product that includes a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform at least one of the following functions:
(a) finding an ideal clock buffer location on a clock tree that minimizes clock skew;
(b) checking whether the ideal clock buffer location overlaps a megacell;
(c) finding a set of megacells that are accessible by a common adjacent side to an overlapped megacell;
(d) defining a megacell boundary that encloses the set of megacells;
(e) finding an initial location where the clock buffer may be placed without overlapping a megacell;
(f) storing the initial location in memory;
(g) finding the next available location where the clock buffer may be placed without overlapping a megacell;
(h) checking whether the next available location is closer to the ideal clock buffer location than the location stored in memory;
(i) replacing the location stored in memory with the next available location found in step (g);
(j) checking whether every available location has been compared with the ideal clock buffer location;
(k) retrieving the location stored in memory; and
(l) placing the clock buffer at the retrieved location.


REFERENCES:
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patent: 5774371 (1998-06-01), Kawakami
patent: 6111448 (2000-08-01), Shibayama
patent: 6127874 (2000-10-01), Wakabayashi et al.
patent: 6266803 (2001-07-01), Scherer et al.
G.M. Blair, Skew-free Clock Distribution for Standard-cell VLSI Designs, IEEE Proceedings on Circuits, Devices, and Systems, pp. 265-267, Apr. 1992.*
P. Ramanathan et al., A Clock Distribution Scheme for Non-symmetric VLSI Circuits, IEEE International Conference on Computer-Aided Design, pp. 398-401, Nov. 1999.

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