Balanced bit line pull up circuitry for random access memories

Static information storage and retrieval – Read/write circuit – Complementing/balancing

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Details

365174, 36523006, 36518901, G11C 700, G11C 1140

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active

052970892

ABSTRACT:
A balancing circuit which may be used as part of a random access memory system for eliminating bit line offset, is disclosed. The balancing circuit contemplated by the invention is capable of supporting rapid memory accesses (such as reads when the memory enters a "read" mode); and simultaneously minimizes the potential for the disturbance of data stored in the memory cells attached to a given bit line pair when the memory is in a "standby" mode following deselect. The invention is particularly useful in connection with the Harper/PNP memory cell arrays.

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patent: 5121357 (1992-06-01), Wiedmann et al.
Marcello, et al., "Bit Current Steering Network" IBM Technical Disclosure Bulletin, vol. 24, No. 1B (Jun. 1981).

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