Static information storage and retrieval – Read/write circuit – Complementing/balancing
Patent
1992-02-27
1994-03-22
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Complementing/balancing
365174, 36523006, 36518901, G11C 700, G11C 1140
Patent
active
052970892
ABSTRACT:
A balancing circuit which may be used as part of a random access memory system for eliminating bit line offset, is disclosed. The balancing circuit contemplated by the invention is capable of supporting rapid memory accesses (such as reads when the memory enters a "read" mode); and simultaneously minimizes the potential for the disturbance of data stored in the memory cells attached to a given bit line pair when the memory is in a "standby" mode following deselect. The invention is particularly useful in connection with the Harper/PNP memory cell arrays.
REFERENCES:
patent: 3789243 (1974-01-01), Donofrio et al.
patent: 4158237 (1979-06-01), Wiedmann
patent: 4302823 (1981-11-01), Gersbach et al.
patent: 4455625 (1984-06-01), Denis et al.
patent: 4555776 (1985-11-01), Masenas, Jr.
patent: 4760561 (1988-07-01), Yamamoto et al.
patent: 4780850 (1988-10-01), Miyamoto et al.
patent: 4813017 (1989-03-01), Wong
patent: 5070482 (1991-12-01), Miyaji
patent: 5121357 (1992-06-01), Wiedmann et al.
Marcello, et al., "Bit Current Steering Network" IBM Technical Disclosure Bulletin, vol. 24, No. 1B (Jun. 1981).
International Business Machines - Corporation
Kaliko Joseph J.
LaRoche Eugene R.
Peterson Jr. Charles W.
Tran Andrew
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