Balanced accuracy for extraction

Details Balanced accuracy for extraction Balanced accuracy for extraction

2005-02-08

2005-02-08

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06854099

ABSTRACT:
A method and system for performing parasitic extraction, wherein the method comprises calculating the minimum output impedance for a network-connected component comprising a plurality of ports thereby producing a labeled impedance, estimating the minimum output impedance for every net, comparing the labeled impedance with the estimated impedance, and selecting the net which needs to be extracted based on a ratio of values of the labeled impedance and the estimated impedance. The step of calculating comprises labeling every port with a minimum size of port impedance, a resistance from a port to power, and a minimum capacitance of a port-net inside the network connected component. The step of estimating comprises using a geometry of segments of the net comprising a summation of area and perimeter values of all the segments of the net, or calculating a resistance over a length of a total net versus an average width of the net.

REFERENCES:
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patent: 5903469 (1999-05-01), Ho
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patent: 6182269 (2001-01-01), Laubhan et al.
patent: 6289412 (2001-09-01), Yuan et al.
patent: 6499129 (2002-12-01), Srinivasan et al.

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