Backward inquiry to lower level caches prior to the eviction of

Details Backward inquiry to lower level caches prior to the eviction of Backward inquiry to lower level caches prior to the eviction of

1996-06-20

1998-10-27

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711122, G06F 1314

Patent

active

058290389

ABSTRACT:
A system and method for reducing the number of writeback operations performed by level two (L2) or higher level cache memories in a microprocessor system having an integrated hierarchical cache structure. Writeback operations of modified victim lines in L2 or higher level caches are cancelled if an associated cache line, having a "modified" status, is located in a lower level cache. In one embodiment of the present invention, writeback operations of modified victim lines in L2 or higher level caches are also cancelled if an associated cache line, having a "clean" status, is located in a lower level cache.

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