Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-01-31
2006-01-31
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S022000, C713S320000, C368S228000
Reexamination Certificate
active
06993680
ABSTRACT:
An object of the invention is to make it possible to secure data retained by a cache memory with high reliability without increasing the size or cost of a storage device. When a host-handling processor and a disk processor have recognized occurrence of a power failure, operation of a storage device is continued for about one minute on DC power that is supplied from a battery module. After a lapse of one minute from the occurrence of the power failure, the host-handling processor interrupts the connection between the storage device and a host. Then, the host-handling processor turns off a SW of a host I/F and the disk processor writes, to an HDD, data that have been written to a cache memory. After completion of this processing, the disk processor turns off a SW of the disk I/F and a SW of the HDD. Then, the disk processor causes the battery module to supply DC power only to the cache memory.
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A. Marquez, Esq. Juan Carlos
Beausoliel Robert
Fisher Esq. Stanley P.
McCarthy Christopher
Reed Smith LLP
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