Backside unlayering of MOSFET devices for electrical and...

Chemistry: electrical and wave energy – Apparatus – Coating – forming or etching by sputtering

Reexamination Certificate

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C204S192340

Reexamination Certificate

active

07993504

ABSTRACT:
A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

REFERENCES:
patent: 3699334 (1972-10-01), Cohen et al.
patent: 4411762 (1983-10-01), Kline
patent: 4446403 (1984-05-01), Cuomo et al.
patent: 4503329 (1985-03-01), Yamaguchi
patent: 4983540 (1991-01-01), Yamaguchi et al.
patent: 5319197 (1994-06-01), Friedhelm
patent: 5354695 (1994-10-01), Leedy
patent: 5589042 (1996-12-01), Robinson et al.
patent: 5653622 (1997-08-01), Drill et al.
patent: 5698474 (1997-12-01), Hurley
patent: 5916424 (1999-06-01), Libby et al.
patent: 5926688 (1999-07-01), Lee et al.
patent: 6211527 (2001-04-01), Chandler
patent: 6263566 (2001-07-01), Hembree et al.
patent: 6346768 (2002-02-01), Proudfoot
patent: 6570170 (2003-05-01), Moore
patent: 6590409 (2003-07-01), Hsiung et al.
patent: 2002/0072308 (2002-06-01), Kane et al.
patent: 2003/0073314 (2003-04-01), Skinner
R. Desplats, F. Beaudoin, P. Perdu, CNC Milling and Polishing Techniques for Backside Sample Preparation,CNES-THALES Laboratory-18 avenue Edouard BELIN-31401 Toulouse Cedex 4-France, pp. 1-9.
R. Livengood, P. Winer, J.A. Giacobbe, J. Stinson, J.D. Finnegan, Advanced Micro-Surgery Techniques and Material Parasitics for Debug of Flip-Chip Microprocessor, Proceeding from the 25th International Symposium for Testing and Failure Analysis, Nov. 14-18, Santa Clara, CA, Intel Corporation, Santa Clara, CA, pp. 477-483.
J.P. Huynh, J.P. Shannon, M. Santana, Jr., T.Y. Chu, M. Gonzalez, Backside Fib Device Modifications Through the Box Layer of an SOI Device, Proceedings from the 28th International Symposium for Testing and Failure Analysis, Nov. 3-7, 2002, Phoenix, AZ, Advanced Micro Devices, Inc., Austin, TX, pp. 403-407.
V. Korchnoi, Dr. A. Fenigstein, A. Barger, Silicon Trenching Using Dry Etch Process for Back Side Fib and Probing, Proceeding from the 26th International Symposium for Testing and Failure Analysis, Nov. 12-16, 2000, Bellevue, WA, Intel Corporation, Israel, pp. 559-565.
P.F. Ullmann, C.G. Talbot, R.A. Lee, C. Orjuela, R. Nicholson, A New Robust Backside FLI-Chip Probing Methodology, Proceedings of the 22nd International Symposium for Testing and Failure Analysis, Nov. 18-22, 1996, Los Angeles, CA, Schlumberger Technologies, San Jose, CA, pp. 381-386.
S. Silverman, R. Aucoin, J. Mallatt, D. Ehrlich, Laser Microchemical Technology: New Tools for Flip-Chip Debug and Failure Analysis, Proceedings from the 23rd International Symposium for Testing and Failure Analysis, Oct. 27-31, 1997, Santa Clara, CA, Revise Inc., Burlington, MA, pp. 211-213.
C-L. Chiang, N. Khurana, D.T. Hurley, K. Teasdale, Proceedings from the 24th International Symposium for Testing and Failure Analysis, Nov. 15-19, 1998, Dallas, TX, Hypervision, Inc., Fremont, CA, Hexfet America, Temecula, CA, 1998 ASM International.
P. Perdu, R. Desplats, F. Beaudoin, Comparative Study of Sample Preparation Techniques for Backside Analysis, Proceeding from the 24th International Symposium for Testing and Failure Analysis, Nov. 12-16, 2000, Bellevue, WA, Toulouse, France, pp. 161-171.

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