Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-12-11
2004-09-14
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S060000, C451S286000, C451S287000, C451S288000
Reexamination Certificate
active
06790125
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacturing of integrated circuits and, in particular, to the surface finishing of integrated circuit die surfaces prior to emission analysis.
2. Description of Related Art
Microprocessor chips or dies are made from semiconductor wafers and contain numerous integrated circuits. Various methods are used for the identification, redesign and process improvements to functioning and non-functioning integrated circuits. These methods include functional characterization of logic integrated circuits for design debug, earlier hardware functionality, reliability qualification assurance, and manufacturing yield learning analysis. Such methods require backside emission microscopy, laser optical beam induced current (OBIC), light induced voltage alteration (LIVA), and picosecond image circuit analysis (PICA). Backside emission microscopy involves detecting photons of light from the recombination and relaxation of electrons and holes, typically during semiconductor failure modes. Common techniques to improve infrared wavelength signal of photons emitted from electron-hole pairs of device junctions is to backside thin substrate of silicon to minimized scattering effects of implant dopant concentrations. A tool and process for machining the backside of a silicon semiconductor for backside emission microscope detection is disclosed in U.S. Pat. No. 5,698,474, the disclosure of which is hereby incorporated by reference.
Current techniques use numerical controlled milling machine followed by various methods of hand polishing, chemical-mechanical polishing (CMP) slurries, wet etching, all aimed to remove machine milling marks and scratches. These techniques are unsatisfactory due to the irregularities in hand polishing or hand held machine surface polishing, and to deficiencies in the slurries associated with chemical-mechanical polishing. The problems are exacerbated by the size of the microprocessor chip or die surface, which may be greater than 15 mm by 15 mm, and up to 30 mm by 30 mm or more.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of polishing a wafer which provides a surface finish which is uniformly planar.
Another object of the present invention is to provide an improved method and tool for removing milling machine marks from die surfaces.
A further object of the invention is to provide a faster time interval for polishing a silicon wafer.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method for preparing a semiconductor die for analysis. The method comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.
In another aspect, the present invention provides a method for polishing a semiconductor surface comprising providing a semiconductor having a surface to be polished, providing a polishing pad for polishing the semiconductor surface, and providing a rotatable spindle for securing the polishing pad. The method includes applying a constant force from the spindle to the polishing pad and urging the polishing pad against the semiconductor surface, rotating the spindle and polishing pad, and polishing the semiconductor surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.
The backside of the die preferably comprises silicon, and the polishing removes portions of the silicon. The backside of the die may also contain silicon oxide, silicon nitride, and/or silicon germanium. Prior to polishing the die backside with the polishing pad, the method preferably includes milling the die backside to remove a desired thickness of the die. The method may further include analyzing the polished backside of the die by emission microscopy.
Preferably, the spindle and polishing pad are rotated at a speed of about 500 to 200 rpm during polishing, and the polishing pad is resilient and deformed during polishing. The method may also include applying a non-reactive slurry between the polishing pad and the die surface during polishing. Preferably, the semiconductor die is secured in a stationary position in a fixture.
In a further aspect, the present invention provides a tool for polishing a semiconductor die comprising a polishing pad for polishing a surface of a semiconductor die, a spindle for securing the polishing pad to a distal end thereof, a constant force actuator on the spindle, the constant force applicator being adapted to provide constant force between the polishing pad and a surface of the die, and a chuck for rotating the spindle.
Preferably, the constant force actuator comprises a spring maintained in compression between the spindle and the polishing pad. The polishing pad is preferably resilient and deformable during polishing.
REFERENCES:
patent: 5273940 (1993-12-01), Sanders
patent: 5635083 (1997-06-01), Breivogel et al.
patent: 5653622 (1997-08-01), Drill et al.
patent: 5698474 (1997-12-01), Hurley
patent: 5868896 (1999-02-01), Robinson et al.
patent: 5916009 (1999-06-01), Izumi et al.
patent: 5925576 (1999-07-01), Peng
patent: 5941758 (1999-08-01), Mack
patent: 6263566 (2001-07-01), Hembree et al.
patent: 9270398 (1997-10-01), None
patent: 10076461 (1998-03-01), None
T. Kane, K. DeVries, M. Tenney, A. Patel,Characterization and Fault Identification of Copper BEOL sub 0.25 &mgr;m Six Level Metal Microprocessor Designs; IBM Advanced Semiconductor Technology Center, pp. 1-6.
Moyra McMamus, Bill Huott, Pia Sanda, Steven Steen, Dan Knebel, Denis Manzer, Steve Wilson, Tony Pelella, Yuen Chan, Stas Polonsky:Picosecond Imaging Circuit Analysis of the IBM G6; IBM T.J. Watson Research Center, IBM S/390 Division, pp. 1-4.
Kane Terence
Miles Darrell L.
DeLio & Peterson LLC
Hail III Joseph J.
International Business Machines - Corporation
McDonald Shantese
Reynolds Kelly M.
LandOfFree
Backside integrated circuit die surface finishing technique... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Backside integrated circuit die surface finishing technique..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Backside integrated circuit die surface finishing technique... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3227196