Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-11-29
2002-05-28
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S014000, C438S121000, C438S613000
Reexamination Certificate
active
06395580
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for conducting a backside failure analysis on a ball grid array (BGA) package that requires a bias voltage input and more particularly, relates to a method for conducting a backside failure analysis on a BGA package that requires a bias voltage input by mechanically removing an IC chip encapsulated in a plastic compound from a substrate, and then polishing by a mechanical method the backside of the IC chip to remove the molding compound and to expose a naked surface of the IC backside and a plurality of bonding wires for connection to probe tips or to wire bonds from a bonder.
BACKGROUND OF THE INVENTION
In the semiconductor fabrication technology, the capability and effectiveness of performing a failure analysis on a semiconductor chip package are very important. When an integrated circuit (IC) chip fails in service, the nature and the cause for such failure must be determined in order to prevent the reoccurrence of such failure in similar products.
An IC chip is normally built on a silicon base substrate with many layers of insulating materials and metal interconnections. This type of multi-layer structure becomes more important in modem IC devices such as high density memory chips where, in order to save chip real estate, the active device is built upwards in many layers forming transistors, capacitors and other logic components.
When an IC device is found defective during a quality control test, various failure analysis techniques can be used to determine the cause of such failure. Two of the more recently developed techniques for performing failure analysis are the infrared light emission microscopy and the light-induced voltage alteration (LIVA) imaging technique. In the infrared light emission light analysis, an infrared light transmitted through a substrate silicon material is used to observe from the backside of an IC the failure mode of the circuit. For instance, at a magnification ratio of 100x, a failure site in the circuitry can be located. The LIVA imaging technique can be used to locate open-circuited and damaged junctions and to image transistor logic states. The LIVA images are produced by monitoring the voltage fluctuation of a constant current power supply when a laser beam is scanned over an IC. A high selectivity for locating defects is possible with the LIVA technique.
Another method that has become more common in failure analysis of IC chips is the scanning optical microscopy (SOM). The high focusing capability of SOM provides improved image resolution and depth comparable to conventional optical microscopy. It is a useful tool based on the laser beam's interaction with the IC. The SOM technique enables the localization of photocurrents to produce optical beam induced current image that show junction regions and transistor logic states. Several major benefits are made possible by the SOM method when compared to a conventional scanning electron microscopy analysis. For instance, the benefits include the relative ease of making IC electrical connection, the no longer required vacuum system and the absence of ionizing radiation effects.
Even though the above discussed techniques are effective in identifying failure modes in IC circuits, the techniques require elaborate and complicated electronic equipment which are generally costly and not readily available in a semiconductor fabrication facility. It is therefore desirable to have available a method and apparatus that can be easily carried out without expensive laboratory equipment such that the apparatus can be installed in any fabrication facilities. One such apparatus utilizes a liquid crystal coating layer for the identification of failure sites in an IC chip. For instance, in the method wherein a liquid crystal layer is used for the identification of failure sites, a liquid crystal material is frequently coated on top of an IC chip or an IC package. A typical test set up is shown in FIG.
1
.
As shown in
FIG. 1
, a typical liquid crystal detection apparatus
10
is provided. The apparatus
10
generally includes a heater
12
and an optical microscope
14
. On a top surface
16
of the heater
12
, an IC package
20
is positioned under the microscope
14
. The IC package
20
may be a plastic quad flat pack (PQFP) or any other packaged IC device. The IC package
20
, shown in
FIG. 1
, is completed with bonding pads
22
and bonding wires
24
. In the middle portion of the package
20
are IC circuits that contain failure sites needed to be identified by a liquid crystal method. In the conventional method, a liquid crystal material is first coated on the top surface
26
of the IC package
20
. The IC package
20
is then positioned on top of the heater
12
which can be heated at a pre-programmed heating rate to a specific temperature. The IC package
20
, together with the coated liquid crystal layer (not shown) is normally heated to a temperature just below the clear/opaque transition temperature of the liquid crystal material. For instance, a suitable temperature would be approximately between about 5° and about 10° below the transition temperature of the liquid crystal. After the IC package
20
is heated to the predetermined temperature, a pre-selected voltage is applied to the IC circuit through bonding wires
24
. The IC circuit, upon receiving such a voltage, heats up at any short or leakage positions. A hot spot is thus generated at each of the locations. The liquid crystal material immediately adjacent, or contacting the hot spots has its temperature raised above its transition temperature and transforms from an opaque state to a clear state. As a result, bright spots in the liquid crystal layer, i.e., on the IC package, show up to indicate the failure sites in the package.
Several drawbacks have been noted in the practice of the liquid crystal detection method. One of the obvious drawbacks is that when testing IC chips of different sizes, a single test board cannot be used for all IC chips. A different test board is required for testing chips of different sizes such that the chip can be mounted on the board for making electrical connections by wire bonding with the conductive leads provided on the test board. Based on the large number of IC chips of different sizes it is a tedious task to supply a large number of test boards that will fit each individual chip. Ideally, a universal test board should be designed such that it will fit different sizes of IC chips for testing.
Regardless which one of the failure analysis techniques is adopted, an IC chip package must be properly prepared with a suitable surface for performing a failure analysis. Since most modern IC chips utilizes at least two or more layers of metal thin films as interconnect layers, the active components of the chip on which the failure analysis is to be performed are usually shielded by the metal interconnect layers. Great difficulties are encountered in performing any of the failure analysis techniques, i.e., the infrared light emission microscopy, the LIVA imaging technique or the SOM technique, which cannot penetrate the layers of metals to detect the failure mode in the circuit.
In another more recently developed package for IC chips, i.e., the lead-on-chip (LOC) package, both the lead frame and the bonding wires are positioned on top of an IC circuit. The LOC package has been used in modern high density memory devices wherein a plurality of finger leads are disposed on and attached to an active surface of an IC chip. The benefits of using a LOC package is that the ratio between the size of an IC chip and the size of a package (which encapsulates the chip) is significantly higher than conventional packages since the mounting area (die pad) is no longer required in a LOC package. A high ratio between the chip size and the package size is very desirable in the ever increasing miniaturization of IC devices. A metal lead frame is normally used in a LOC package which substantially covers the active device.
Attempts have been made by others to pe
Collins D. M.
Picardat Kevin M.
Taiwan Semiconductor Manufacturing Company , Ltd.
Tung & Associates
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