Backside device deprocessing of a flip-chip multi-layer...

Details Backside device deprocessing of a flip-chip multi-layer... Backside device deprocessing of a flip-chip multi-layer...

1998-07-30

2001-01-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C438S015000, C438S016000, C438S017000, C438S018000, C438S108000, C257S778000

Utility Patent

active

06168960

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multi-layer integrated circuit (IC) devices, and more particularly to device deprocessing for analysis of a multi-layer integrated circuit device from a backside of the device.
BACKGROUND OF THE INVENTION
For flip-chip, multi-layer IC devices, debugging for physical defects in the IC is difficult due to having to approach the desired layers from the backside of the device.
FIG. 1
illustrates a sideview of a portion of a typical flip-chip configuration. As shown in
FIG. 1
, an IC device
10
is coupled to a ceramic package
12
(e.g., a C4 package) via solder bump
14
. The solder bump
14
acts as a chip-to-carrier interconnect to attach the IC device
10
to the ceramic package
12
and to mate with corresponding pad patterns to form the necessary electrical contacts between the circuit(s) of the IC device
10
and pins of the package
12
. To analyze the IC device
10
, the thick silicon substrate
16
, e.g., on the order of 530 microns (&mgr;m) thick, which is the top layer seen from the backside of the IC device
10
, must be reduced.
A common approach to reduce the silicon thickness is to utilize mechanical polishing of the device. The mechanical polishing used from the backside removes the silicon and creates a very thin device. The reduced thickness allows utilization of an infrared (IR) optical device to view the device. Unfortunately, the thin device created by polishing is difficult to handle and subsequently utilize in further device analysis, which normally requires the removal of the device from the package to perform well-established delayering techniques from a frontside of the device. Breakage of the device often occurs due to the thinness of the device and brittleness of the silicon. Thus, the process is highly problematic and significantly time-consuming.
Accordingly, a need exists for efficient device analysis from the backside for flip-chip IC devices. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides for device deprocessing from the backside in flip-chip multi-layer integrated circuits. In an exemplary method aspect, the method includes reducing a first backside layer of the multi-layer integrated circuit to a predetermined thickness, and exposing an active region of the multi-layer integrated circuit to allow device analysis of the multi-layer integrated circuit. The method further includes removing a metal layer beneath the active region to expose interlayer dielectric material, performing a bulk delayering of the interlayer dielectric material to expose a next metal layer, and continuing to delayer the multi-layer integrated circuit layer-by-layer from the backside for analysis of the multi-layer integrated circuit.
Through the present invention, more efficient device analysis is achieved for flip-chip devices. The present invention achieves effective delayering from the backside, thus avoiding problems associated with device removal for frontside delayering. These and other advantages of the aspects of the present invention will be more fully understood in conjunction with the following detailed description and accompanying drawings.


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