Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-08
2002-10-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S667000, C438S675000
Reexamination Certificate
active
06468889
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, a backside contact for an integrated circuit device and a method for fabricating the backside contact.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
In the fabrication of integrated circuits, many layers are formed atop one another in “sandwich” fashion. These layers include semiconductor materials, insulating materials, and conductive materials, for example, metals. A common integrated circuit may contain as many as ten to twenty different layers, and as many as six or seven of those layers may be metal layers. Generally, the metal layers are patterned to form electrical interconnects, or conductors, that carry electrical power for distribution throughout the integrated circuit, as well as signals, for example, control signals, address signals and data signals.
FIG. 1
illustrates a cross-section of a simple form of an integrated circuit device. A semiconductor substrate
10
, which may be silicon or other suitable material, forms the foundation upon which the integrated circuit will be built. Transistors may be formed atop the substrate
10
and, for example, such a transistor may comprise a gate
11
. The gate
11
, which is typically separated from the semiconductor substrate by a thin insulating layer (not shown), may comprise a conductive material, such as a doped polycrystalline silicon, or polysilicon. As is well known in the art of semiconductor device fabrication, a polysilicon material may be deposited or otherwise formed over the surface of the substrate
10
(typically separated therefrom by a thin oxide layer) and thereafter patterned to form transistor gates.
Overlaying the substrate
10
and the gate
11
may be a dielectric, or insulating, layer
12
, for example, a layer of silicon dioxide. Commonly in the fabrication of semiconductor integrated circuits, above the insulating layer
12
will be formed a layer of electrically conductive material that is patterned and etched to form conductive interconnects
13
and
14
. Typically, the conductive interconnects will be formed from a metal. The interconnect
13
may be electrically coupled to the gate
11
by a conductive material
15
, for example, a metal. As is well understood in the field of semiconductor integrated circuit fabrication, a via may be formed through the dielectric layer
12
, and the via may be filled with a conductive material, for example, a metal, before or during the formation of the conductive layer used to form the interconnects
13
and
14
. Thus, electrical interconnections may be made between conductive layers at different levels of the integrated circuit device.
Overlaying the interconnects
13
and
14
will be a second dielectric, or insulating, layer
16
. As in the case of layer
12
, layer
16
may comprise a silicon dioxide or other suitable material. Also, layers
12
and
16
, as well as additional dielectric layers discussed below, may be formed on the integrated circuit by any suitable known technique, for example, CVD, spin-on techniques, etc. Atop the dielectric layer
16
, another conductive layer, again, for example, metal, may be formed and patterned to create further interconnects
20
and
21
. As illustrated in
FIG. 1
, interconnects
14
and
20
may be electrically coupled by way of conductive material
19
through a via. Overlaying the interconnects
20
and
21
is yet another dielectric, or insulating, layer
22
, which may also comprise a suitable insulating material, for example, silicon dioxide.
Additional conductive layers and dielectric layers may be formed atop the insulating layer
22
to form, for example, interconnects
23
,
24
,
26
and
29
, and dielectric layers
25
and
28
. When fabrication of the integrated circuit is essentially complete, contact pads, for example pad
31
, will be formed atop the integrated circuit. These contact pads will be coupled to various points in the integrated circuit, for example, interconnect
13
by way of path
32
and lead
33
. Path
32
may be formed by etching through at least some of the layers overlaying the substrate
10
. For example, as illustrated in
FIG. 1
, path
32
is etched through each of the dielectric layers
16
,
22
,
25
and
28
to facilitate an electrical connection between lead
33
and contact
31
and the interconnect
13
. Likewise, throughout the integrated circuit device, similar paths
32
may be etched through various of the layers of the integrated circuit device to contact selected electrical interconnects at the various metal, or conductive, layers. The contact pad
31
, lead
33
and path
32
may facilitate the supply of electrical power to the integrated circuit, or they may provide a route for signals into and out of the integrated circuit. For example, DC voltages may be applied to various portions of the integrated circuit by means of contact pads
31
, leads
33
and paths
32
. Also, data input and output signals, address signals and a variety of control signals may be applied to or retrieved from the integrated circuit by means of contact pads
31
, leads
33
and paths
32
.
As illustrated in
FIG. 1
, electrical paths
32
between the contact pads
31
and the various metal layers are routed from the top surface
34
of the integrated circuit device, down through the various dielectric layers, to the particular conductive layer or interconnect to be contacted. As integrated circuits become more complex, they become more dense. Consequently, the space between devices, including interconnects, on the integrated circuit becomes smaller. Moreover, as more and more conductive layers are used in the fabrication process, the routing of the contact paths
32
to the selected layer or interconnect becomes more complex and constricted. In addition, although efforts have been made to reduce power consumption, many modern devices require more electrical current than did their predecessors, and these larger electric currents are typically transported by way of the electrical paths
32
.
To exacerbate the situation, electrical power typically must be routed to the lowest metal layers in the integrated circuit. In those situations, routing of the contact paths
32
presents numerous problems. For example, because of the small space between adjacent devices and interconnects in the integrated circuit, the cross-section of the electrical path
32
must be small. As the integrated circuits become more complex and utilize more layers, the length of the electrical path
32
becomes longer. As the cross-section of the electrical path
32
decreases and its length increases, it presents a greater resistance to the flow of current, resulting in, among other things, more heat generated.
The present invention
Iacoponi John A.
Miethke John C.
Advanced Micro Devices , Inc.
Lytle Craig P.
Smith Matthew
Williams Morgan & Amerson
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