Backside bus vias

Details Backside bus vias Backside bus vias

1999-07-26

2001-10-09

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With electrical contact in hole in semiconductor

C257S698000, C257S774000, C257S772000, C257S773000, C257S780000, C257S777000, C257S779000, C257S680000

Reexamination Certificate

active

06300670

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to off-chip buses for integrated circuits, and more specifically to forming a bus via in an integrated circuit for connecting bus conductors to off-chip contact pads on the backside of the die containing the integrated circuit.
2. Description of the Prior Art
A backside bus is a bus within an integrated circuit having conductors connected to contact pads on the backside, or the side opposite that on which active devices are formed, of a substrate. There are a variety of circumstances under which a backside bus is useful in integrated circuitry. Sensor devices, whether for image detection, state switches, or chemical sensors, can particularly benefit from backside buses, which increase the front side surface area of a die available for sensors rather than for contact pads. Pad limited designs, in which the integrated circuit is restricted by the number of contact pads which may be fit along the periphery of a given die, may also benefit significantly from backside buses.
Backside buses may be fabricated by forming through-holes within a substrate for a conductive via connecting a contact on the active side of the substrate with a contact on the backside of the via. A separate through-hole is thus required for each bus conductor, such that the substrate area required for conductor is substantial. Additionally, the challenges of filling a through-hole or otherwise reliably establishing an electrical connection from one end of the through-hole to the other are significant.
It would be desirable, therefore, to provide a technique for implementing backside buses in an integrated circuit with minimal use of substrate area and reliable formation of electrical connections between the active devices on the active side and the contact pads on the backside.
SUMMARY OF THE INVENTION
Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary. The backside bus is beneficial for sensor devices, leaving more room for sensor circuitry on the active side and simplifying packaging, for pad-limited designs, and for forming stackable integrated circuits.


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David Francis and Linda jardine, “A Visible Way to Use Chip-Scale for Discrete Devices”, Chip Scale Review, Mar./Apr. 1999, pp. 58-59.

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