Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus expansion or extension
Reexamination Certificate
2001-03-29
2004-12-28
Thai, Xuan M. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus expansion or extension
C370S201000, C361S201000, C379S394000, C340S315000
Reexamination Certificate
active
06836810
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to system interfaces for backplane technology. More particularly, the present invention relates to bridges and switching systems for establishing transmission interfaces among circuit boards or cards installed in computing device backplanes. The system enables the insertion of a greater number of cards in a backplane topology than has heretofore been possible.
2. Description of the Prior Art
Standards have been established for the architecture of the hardware employed to enable the exchange of electrical signals among processing devices. The processing devices include integrated circuit systems built on and using printed circuit boards by an increasingly wide array of suppliers. The architecture standards ensure that the various devices will, in fact, be able to communicate with one another as well as with central processing units that control the operation of such peripheral devices. These peripherals include, but are not limited to, printer interfaces, video, audio, and graphics interfaces, memory, external communications interfaces, or any other sort of discrete device performing particular computer-related functions.
The circuit boards associated with the peripherals may be activated upon connection with a primary hardware board, often referred to as a motherboard. The motherboard establishes the interconnection of the central processing unit, power, memory structures, and a backplane bus. The backplane bus is a primary communication interface coupling line having connections to one or more slots or sockets in parallel into which the peripheral circuit boards may be inserted. The slots include physical connectors and input/output interfaces to establish reception and transmission of signals among all devices coupled to the motherboard through the backplane bus. It is the architecture of the backplane bus that establishes the interface architectures required for the peripheral boards so that communication can occur between all peripherals and the central processing unit in an organized manner.
Several communication hardware protocols have been developed, a number of which have been or are being phased out as being inadequate to support the faster signal exchange rates and increased bandwidth required by newer applications. One of the first such architecture protocols that remains in use on older motherboards is the Industry Standard Architecture (ISA). ISA is an expansion bus slot configuration that accepts plug-ins for peripherals including sound and video displays, for example. Earlier ISA slots were of 8-bit configuration but they are mainly 16-bit slots now. A modified version of ISA, Extended ISA (EISA) was developed to extend the bus capacity to 32-bit with essentially the same convention applied to the ISA backplane slot architecture. Unfortunately, it is designed to run at the relatively slow ISA rate of 8 MHz clocking. In today's computing world, that is often too slow.
Although ISA had been the primary standard, the Peripheral Component Interconnect (PCI) bus is now the most frequently implemented interface architecture. Although it continues to replace ISA, that architecture will be used by peripherals designers for as long as computing devices including ISA slots remain in use. PCI provides a relatively high-speed data path (33 MHz) among connected boards. PCI Local Bus is an open architecture specification that allows applications designers greater freedom in interface formation. PCI provides “plug and play” capability in that any peripherals with PCI-based interfaces are automatically configured at start up and therefore generate little to no delay for the central processing unit to establish communication. One advantage of PCI is that it permits the sharing of IRQs. An IRQ (Interrupt ReQuest) signals the central processing unit that activity associated with a peripheral device has started or ended. Since motherboards are configured with only a limited number of IRQ lines, any interface architecture that requires dedicated IRQ lines is necessarily limited. Such is the case with ISA, but not with PCI. For that reason, PCI architecture is ordinarily the first choice.
While the PCI design is an improvement on ISA, it has a history of problems with edge connectors, poor thermal characteristics, and limited interface (input/output—I/O) capability. In fact, PCI backplane configuration is limited to only four slots. That is due in part to the need to resolve signal reflections or noise at the board-to-backplane interface. Subsequent developments to double the clock rate to 66 MHZ and to increase the bus width accommodated some of the reflection problems, resulting in a doubling to eight of the number of available PCI slots. That improvement established a new slot architecture referred to as eXtended PCI (PCI-X) architecture. Unfortunately, while providing more slot availability, PCI-X continues to suffer from the same problems associated with PCI.
Because of interconnection limitations associated with the PCI architectures, there are limits on the number of peripheral devices that may be coupled together. Bridging together two PCI-based backplanes may increase slot capacity; however, that simply increases the size
umber of the computer device required to establish desired functionality. It also introduces its own latency and transmission complications. As a result, the Personal Computer Industrial Computer Manufacturing Group (PICMG) developed a standard to address these problems with the PCI functionality. The PICMG combined the architecture of the Eurocard interface with a passive backplane (that is, no active devices to regulate signal propagation, only passive elements), and a high-quality, high-density pin-and-socket arrangement to make improvements. All motherboard components are hence moved from the now passive backplane to a Single Board Computer (SBC) card to be present in the system slot of the passive backplane. The relatively new connection architecture, identified as COMPACTPCI, a registered trademark of PCI Industrial computers manufacturers Group (hereinafter referred to a cPCI), improved the peripheral board-to-backplane impedance match, thereby reducing unwanted reflections at that interface. cPCI is designed to be a more robust interface connector to establish solid electrical connections.
The improvements established in cPCI generated the ability to provide eight PCI slots at a 33 MHz-lock rate. However, at higher clock rates the number of available slots is reduced because of the reflective wave signaling technology being used. Using reflected wave technology means the signal travels at half its intended amplitude until it reaches the end of the backplane where it doubles to its intended amplitude and propagates back down the backplane to its point of origin. This round trip delay physically limits the backplane to the number of slot connections it can have for a given clock frequency. The cPCI architecture at 66 MHz available in typical computing systems has thus been limited to five open slots.
What is needed is a backplane architecture and interface system that allows for a greater number of slots available for peripheral connections without increasing the footprint of the backplane. Further, what is needed is a backplane architecture and related system that expands the number of slots available without requiring bridging from one backplane to another. Yet further, what is needed is such a backplane architecture and related system that does not compromise the integrity and rate of signal reception and transmission. Still further, what is needed is such a backplane architecture and related system that may optionally be compatible with legacy interface architectures including, but not limited to, ISA.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a backplane architecture and interface system that provides for an increase in the number of slots available for peripheral connections without increasing the footprint of the backpla
Klem R. Craig
Poirier Carl R.
Cesari and McKenna LLP
Fairchild Semiconductor Corporation
Mason Donna K.
Paul, Esq. Edwin H.
Thai Xuan M.
LandOfFree
Backplane system using incident waveform switching does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Backplane system using incident waveform switching, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Backplane system using incident waveform switching will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3289507