Backplane physical layer controller

Details Backplane physical layer controller Backplane physical layer controller

2000-09-19

2003-07-22

Auve, Glenn A. (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S107000, C710S015000, C710S016000, C710S062000, C711S202000

Reexamination Certificate

active

06598111

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor devices and systems and specifically to backplane physical layer controllers.
BACKGROUND OF THE INVENTION
Electronic systems include a number of components that perform various functions. These components must be interconnected either by connecting individual components together and/or by connecting groups of components to a bus. Numerous varieties of buses can be used in systems utilizing a bus to connect components. For example, a parallel bus would include more than one data line so that multiple bits of data can be transferred simultaneously. In a serial bus, a single data line is used to carry data between devices sometimes in conjunction with a line to carry the clock signal.
One type of serial bus is specified by IEEE-Std-1394-1995. See
IEEE Standard for a High Performance Serial Bus
, Institute of Electrical and Electronics Engineers, Aug. 30, 1996. This standard describes a high-speed, low-cost serial bus suitable for use as a peripheral bus or as a secondary control backup to parallel back-plane buses. This standard is hereby incorporated herein by reference.
FIG. 1
shows a system block diagram for a single node on a backplane bus system
10
. As shown in the figure, 1394 link layer controller
12
is coupled to a host interface and provides digital data to a 1394 physical layer controller
14
. The 1394 physical layer controller
14
provides the signaling for the 1394-compliant bus to transceiver
16
. The transceiver
14
is coupled to the bus (not shown). A 1394 backplane physical layer controller
14
is available from Texas Instruments Incorporated as part number TSB14C01A, which is described by the data sheet entitled “TSB14C01A, TSB1401AI, TSB14C01AM 5-V IEEE 1394-1995 Backplane Transceiver/Arbiter”, Texas Instruments Incorporated, 1999, pp. 1-30, which is incorporated herein by reference.
SUMMARY OF THE INVENTION
In one specific embodiment, the present invention is related to a later version 1394 backplane physical layer controller that can be used to replace the TSB14C01A device. In particular, this specific embodiment includes a register set that allows software written for the previous generation 14C01A to be used with no changes, while also allowing new functionality to be implemented in a software transparent way. This involves designating a particular bit that can be set to a logical “1” so that a user can determine whether the later version device is present in the system, or more typically so that software developed for a particular application can determine whether the later version device is present in the system.
In one aspect, the present invention discloses a method of determining whether a semiconductor device comprises a first version device or a second version device. In the preferred embodiment, both the first version device and the second version device include a register set with a plurality of registers. In the first version device, one of the registers is accessible by a first address and includes at least one reserved bit. In addition, the first version device is decoded in such a manner that reading from a second address nonetheless causes reading from the accessible register. To determine whether the first or second version device is present, the second address is used to read from the reserve bit location. If the bit that is read in is a logical
37
1”, one can determine that the semiconductor device comprises a second version device and take advantage of it's expanded capabilities If the bit is read as a logical “0”, the original version part is present and only the older functionality may be accessed.
In one particular implementation relating to backplane physical layer controllers, the device includes a plurality of eight-bit registers. These registers are decoded by four-bit addresses. At least one of the seventh or eighth bits of the register addressed by the four-bit address “0010” is permanently programmed with a logical
37
1”. This bit(s) can be used to differentiate between the original and later version devices while not affecting operation of software that only comprehends the original version device.


REFERENCES:
patent: 4736290 (1988-04-01), McCallion
patent: 5577050 (1996-11-01), Bair et al.
patent: 6185622 (2001-02-01), Sato
TSB14C01A, TSB14C01A1, TSB14C01AM 5V IEEE 1394-1995 Backplane Transceiver/Arbiter, Texas Instruments, Inc. SGLS 107A—Feb. 1999—Revised Nov. 1999.
IEEE 1394a Features Supported by TI TSB41LV0x Physical Layer Devices—Texas Instruments Application Report: SLLA019, Mixed Signal Logic Products BuS Solutions Group, Dec. 1998.
“Validation of a Link Layer Synthesizable Core—a prototyping case study”, Prasad, P.G., Rapid System Prototyping, 2000. Proceedings. 11th International Workshop. pp. 208-213.

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