Background execution of universal serial bus transactions

Details Background execution of universal serial bus transactions Background execution of universal serial bus transactions

2000-01-25

2003-12-02

Vo, Tim (Department: 2189)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S266000

Reexamination Certificate

active

06658515

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer systems. More particularly, the present invention is directed to a communication protocol for transmitting data over a universal serial bus while a computer is in the system management mode.
2. Description of the Background Art
Referring to
FIG. 1
typical computer systems, such as computer
14
, includes one or more system buses
22
placing various components of the system in data communication. For example, a microprocessor
24
is placed in data communication with both a read only memory (ROM)
26
and random access memory (RAM)
28
via the system bus
22
. The ROM
26
contains among other code, the Basic Input-Output system (BIOS) which controls basic hardware operation such as the interaction with peripheral components such as disk drives
30
and
32
, as well as the keyboard
34
. The RAM
28
is the main memory into which the operating system and application programs are loaded and affords at least
32
megabytes of memory space. The memory management chip
36
is in data communication with the system bus
22
to control direct memory access (DMA) operations. DMA operations include passing data between the RAM
28
and the hard disk drive
30
and the floppy disk drive
32
.
Also in data communication with the system bus
22
are various I/O controllers: a keyboard controller
38
, a mouse controller
40
and a video controller
42
. The keyboard controller
38
provides a hardware interface for the keyboard
34
, the mouse controller
40
provides the hardware interface for a mouse
46
, or other point and click device, and the video controller
42
provides a hardware interface for a display
48
. Each of the aforementioned I/O controllers in data communication with an interrupt controller over an interrupt request line. The interrupt controller is in data communication with the processor to prioritize the interrupts it receives and transmits the interrupt requests to the processor. A drawback with the aforementioned architecture is that a limited number of interrupt request lines are provided. This limited the number of I/O devices that a computer system could support.
A Universal Serial Bus (USB) specification has been developed to increase the number of peripheral devices that may be connected to a computer system. The USB specification is a proposed standard recently promulgated by a group of companies including Compaq Computer Corporation, Digital Equipment Corporation, International Business Machines Corporation, Intel Corporation, Microsoft Corporation, and Northern Telecom Limited. Described below are various aspects of the USB relevant to a complete understanding of the present invention. Further background concerning the USB may be obtained from USB Specification, Revision 1.1.
The USB is a serial bus that supports data exchanges between a host computer and as many as 127 devices on a single interrupt request line. This provided beneficial, especially when employed with processors that supported Intel's System management Mode architecture, such as Intel's Pentium® line of processors. Specifically, it was found that effectuating USB transactions in a processor's real-address mode limited the software platforms that may be supported. Many of the software platforms remapped the interrupt vector table thereby frustrating transactions over the universal serial bus. As a result, it is standard in the computer industry to effectuate USB transactions when the processor operates in the system management mode (SMM).
A system management interrupt (SMI) applied to the SMI pin of the processor invokes the SMM mode. The SMI results from an interrupt request sent by, inter alia, a USB controller. In response, the processor saves the processor's context and switches to a different operating environment contained in system management RAM (SMRAM). While in SMM, all interrupts normally handle by the operating system are disabled. Normal-mode, i.e., real-mode or protected-mode, operation of the processor occurs upon receipt of a resume (RSM) on the SMI pin. As can be readily seen, all USB transactions are associated with a common interrupt line, namely, the SMI pin.
To facilitate communication between the computer system and 127 peripheral devices over a common serial line, the USB specification defines transactions between a host in data communication with a plurality of devices over interconnects. The USB interconnect defines the manner in which the USB devices are connected to and communicate with the USB host controller. There is generally only one host on any USB system. A USB interface to the host computer system is referred to as the host controller. The host controller may be implemented in a combination of hardware, firmware, or software. USB devices are defined as (1) hubs, which provide additional attachment points to the USB, or (2) functions, which provide capabilities to the system; e.g., an ISDN connection, a digital joystick, or speakers. Hubs indicate the attachment or removal of a USB device in its per port status bit. The host determines if a newly attached USB device is a hub or a function and assigns a unique USB address to the USB device. All USB devices are accessed by a unique USB address. Each device additionally supports one or more endpoints with which the host may communicate.
FIG. 2
shows a computer system that employs a universal serial bus. The host computer
50
includes the I/O driver
52
, a USB driver
54
and USB interface logic circuit
56
. The I/O driver
52
continues to model the I/O device
58
as a group of registers. To access a hardware register in I/O device
58
, however, the I/O driver
52
first passes its read or write data request to the USB driver
54
that coordinates construction and transmission of the Token, Data and Handshake packets required by USB protocol for transferring data to or from the I/O device
58
. The CPU with USB port (device interface)
60
is connected to I/O device
58
and is configured by firmware
62
to act as an interface allowing I/O device
58
to communicate with the host via the USB. Device interface
60
receives and decodes incoming packets (e.g. host generated Token packets) and generates complimentary Data or Handshake packets needed to complete a data transfer between I/O device
58
and host computer
50
. A drawback with USB transactions is each requires a great amount of bandwidth.
Recognizing the aforementioned problem with USB transactions, U.S. Pat. No. 5,987,530 to Thomson discloses an apparatus and method for caching data in a universal serial bus (USB) system that reduces both the response time and the data traffic between the host computer and I/O device. The host computer is coupled to the I/O device via a USB system. The host computer includes a data cache for storing data retrieved from the I/O device. The data cache allows data to be returned to the host computer upon request without accessing the I/O device via a USB transaction. A cacheability look-up table and cache table is provided to ensure the integrity of data returned to the host computer. Requested data is returned from the I/O device if the cacheability look-up table indicates the requested data is noncacheable. Data is returned from the data cache if the cache table indicates the requested data is available in the cache as valid data. If the cache table indicates the requested data is not available in the cache as valid data, the requested data is returned from the I/O device along with data stored in predetermined I/O device addresses. The additional data is stored in the cache for subsequent access by the host computer. However, the aforementioned system requires the processor associated with the host computer to be in the system management mode for a significant amount of time which may adversely the operating system and other time sensitive applications.
What is needed, therefore, is a technique for effectuating USB transactions with a processor employing the SMM architecture while minimizi

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