Background-calibrating pipelined analog-to-digital converter

Details Background-calibrating pipelined analog-to-digital converter Background-calibrating pipelined analog-to-digital converter

2003-07-23

2004-11-23

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S150000, C341S120000

Reexamination Certificate

active

06822601

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to digital electronics, and more specifically, to a background calibrating pipelined analog-to-digital converter.
2. Description of the Prior Art
Pipelined analog-to-digital converters (ADCs) are widely used in applications such as video imaging systems, digital subscriber loops, Gigabit Ethernet transceivers, and wireless communications. Pipelined analog-to-digital (A/D) conversion offers a good trade-off among power, speed, and integrated circuit die area, and is suitable for implementing high-resolution ADCs operating at sampling frequencies in the order of megahertz.
FIG. 1
illustrates a state-of-the-art pipelined ADC
10
. The ADC
10
includes a series of multiplying digital-to-analog converter (MDAC) stages
12
,
14
,
16
, which may or may not be identical, and an encoder
18
. The first MDAC stage
12
receives an analog signal V
1
and outputs a digital code D
1
representative of the analog signal V
1
according to a predefined precision. Successive stages
14
,
16
output digital codes D
2
, D
3
according to successive amplified residual signals V
2
, V
3
of the first and second stages
12
,
14
respectively. Each successive stage digitizes the residue of the previous stage, so accordingly, the digital output D
1
of the first stage
12
contains the most significant bits (MSBs) while the output D
p
of the last stage
16
contains the least significant bits (LSBs). The encoder
18
arranges the outputs D
1
, D
2
, D
3
of the stages
12
,
14
,
16
to produce a consistent digital representation D
0
of the input analog signal V
1
.
FIG. 2
illustrates a typical MDAC
20
used for the MDAC stages
12
,
14
,
16
of the ADC
10
of FIG.
1
. The MDAC
20
includes an internal ADC
22
, a digital-to-analog converter (DAC)
24
, an adder
26
, and an amplifier
28
. In operation, an analog input V
j
received from a previous stage (or as an input signal itself) is quantized by the ADC
22
producing a digital code D
j
that is an estimation of V
j
. The DAC
24
generates a corresponding analog signal V
j
da
(D
j
) that is then subtracted from the input signal V
j
by the adder
26
. The residue outputted by the adder
26
is amplified by the amplifier
28
according to a gain factor G
j
. The output V
j+1
of the MDAC
20
can be described as follows:
V
jH
=G
j
×[V
j
−V
da
(D
j
)]  (1)
Accordingly, the input of the pipelined ADC
10
can then be expressed as:
V
1
=
V
1
do
+
V
2
do
G
1
+
V
3
do
G
1
⁢
G
2
+
⋯
+
V
p
do
G
1
⁢
G
2
⁢
 
⁢
⋯
⁢
 
⁢
G
p
-
1
+
Q
(
2
)
where Q=V
P+1
/(G
1
G
2
. . . G
P
) is the quantizing error of the entire A/D conversion. The encoder
18
of
FIG. 1
calculates the digital output D
0
by subtracting Q from V
1
. The signals V
j
da
and gains G
j
are design parameters. In addition, it is well known that the conversion characteristics of the internal ADC
22
in the pipeline stages
20
have no effect on the digital output D
0
.
In CMOS applications, most A/D pipeline stages are realized with switched-capacitor (SC) MDACs, which include comparators, operational amplifiers (opamps), switches, and capacitors as described above.
FIG. 3
shows a prior art radix-2 1.5 bit SC MDAC
30
having a conversion characteristic as illustrated in FIG.
4
. The MDAC
30
includes comparators
32
,
34
, an encoder
36
, switches
38
, first and second capacitors
40
,
42
having respective capacitances C and C, and an operational amplifier
44
. During a sample phase, when a first clock is high, the switches
38
marked
1
are exclusively closed, and the signal V
j
is sampled on the first and second capacitors
40
,
42
. Accordingly, the digital code output is determined as −1, 0, or +1 according to the comparators
32
,
34
comparing the signal V
j
with +0.25V and −0.25V
r
references respectively. Conversely, during a hold phase, when a second clock is high, the switches
38
marked
2
are exclusively closed. During the hold phase, the output V
j+1
can be expressed as:
V
j
+
1
=
(
1
+
C
s
C
f
)
×
[
V
j
-
C
s
C
s
+
C
f
⁢
V
p
·
D
j
]
(
3
)
assuming linear behavior of the capacitors
40
,
42
, and an ideal operational amplifier
44
with infinite DC gain and zero input offset voltage. In practical application, the capacitances C
f
and C
s
of the capacitors
40
,
42
are desired to be the same. However, due to capacitance mismatches (C fnot equal to C) and input offset voltage of the operational amplifier
44
in implementation, the pipelined ADC
10
must be calibrated for accurate results. Regarding calibration, there is a fundamental trade-off between ADC operation speed and accuracy, which depends on the matching properties of devices such as MOSFETs and capacitors. The accuracy of an MDAC is dictated by the input offset voltages of the comparators and the operational amplifier, and the exact values of the capacitor ratios. To overcome this speed-accuracy trade-off, several self-calibration techniques have been developed. Although the calibration can be performed in the analog domain, entirely digital approaches are preferred in deep sub-micron technologies, due to reduced cost of added digital circuitry. In addition, in digital self-calibration schemes the necessary modification to the MDACs is noncritical, and thus, the analog signal paths suffer little performance degradation.
Conventional self-calibration schemes require reconfiguration of MDACs, which cannot be performed without interrupting normal A/D operation. Thus, in applications that can afford little idle time, ADCs are calibrated only during an initial power-on state. Any power-on calibration may later become invalid because of variations in supply voltage and temperature. To address this problem, several background calibration schemes have been developed that enable an ADC to continuously calibrate internal MDACs to track environmental changes while simultaneously performing normal conversion without resolution degradation.
There are several well-known approaches to background calibration. The “skip-and-fill” algorithm randomly skips A/D cycles to calibrate the MDACs and fill in the missing outputs by nonlinear interpolation, as described in U.K. Moon and B.S. Song, “Background digital calibration techniques for pipelined ADCs”, IEEE Trans. Circuits Syst. II, vol. 44, pp. 102-109, February 1997 and S. U. Kwak, B. S. Song, and K. Bacrania, “A 15-b, 5-Msample/s lowspurious CMOS ADC”, IEEE J. Solid-State Circuits, vol. 32, pp. 1866-1875, December 1997, which are incorporated herein by reference. However, the bandwidth of the input signal needs to be limited for the interpolator to achieve good results. Moreover, if a multi-bit MDAC is used in a pipeline stage, it is possible to estimate the MDACs conversion errors in normal A/D operation using information on the MDACs mismatch pattern. But, without the MDACs gain error information, this approach is only suitable for high gain pipeline stages.
Background calibration can also be achieved by using an extra MDAC to replace the one under calibration, as described in J. M. Ingino and B. A. Wooley, “A continuously calibrated 12-b, 10-MS/s, 3.3V A/D converter”, IEFE J. Solid-State Circuits, vol. 33, pp. 1920-1931, December 1998, which is incorporated herein by reference. However, the complexity of the required analog switching scheme can degrade speed performance of the analog signal path.
Another scheme proposed in J. Ming and S. H. Lewis, “An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration,” IEEE J. Solid-State Circuits, vol. 36, pp. 1489-1497, October 2001, which is incorporated herein by reference, is only capable of correcting gain error while adding significant analog and digital hardware.
Finally, an example of a self-calibrating reversible pipeline ADC/DAC is disclosed in U.S. Pat. No. 5,929,796, which is incorporated herein by reference.
The conventional background c

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