Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-30
2001-10-23
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S132000, C257S529000
Reexamination Certificate
active
06306746
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the manufacture of semiconductor devices such as transistors, diodes and integrated circuits. More specifically, this invention relates to a process for forming fuses in integrated circuits.
BACKGROUND OF THE INVENTION
Semiconductor memories are becoming increasing dense; in terms of the number of bits, a single memory chip is approaching the gigabit range. Concurrent with the increase in memory capacity, the dimensions of the circuit components are decreasing. Consequently, the push for more capacity in a smaller space puts pressure on maintaining yield and reducing cost.
One approach to improving yield and cost factors involves the use of built-in redundancy cells for replacement of memory arrays. During testing, if a defective cell is found, one of the built-in redundancy cells is configured to replace it. In one well-known process, fuses are used to provide such redundancy in semiconductor memories. If a semiconductor memory is found to have a small number of defective bits, these defects can be effectively overcome by exchanging the cells containing the faulty bit locations with spare cells especially designed for this purpose. The addresses of the cell(s) exchanged, as provided by a designated row and column address, are programmed into the memory circuitry during test. This is commonly done by opening (e.g., by “blowing” open the fuses) a number of fuses in a special section of the circuit. The fuses can be opened electrically, but it is usually more convenient to open them by subjecting the fuse to a high-intensity focused laser beam on a special probing system.
Any conductive material can be potentially used for the fusible element. For ease of incorporation into an existing integrated circuit, polysilicon, which is also commonly used for the gate electrode, is used for the fusible element. The polysilicon may be N-type or P-type depending upon the polarity of the transistor structure. A metal layer is also often used for the fusible element due its lower inherent resistance, which allows for faster reading of the fuse and, therefore, faster memory access. The particular composition of the metal depends upon the process. For example, a “metal” in a modern sub-micron process may be a “sandwich” of layers. The bottom layer has about 200 Å of titanium, a middle layer of 5000 Å of an aluminum/copper alloy and a top layer of about 300 Å of titanium nitride. Depending on the specifics of the process, other types of alloys and configurations may be used. When the fuse is opened with the laser beam, a great deal of energy is transferred into the fuse, causing a rapid rise in temperature and vaporization of at least part of the fuse. The force of the blast forcibly expels vaporized parts of the fuse. In this way, the fuse changes from a conductive link to a non-conductive link. The ease and reproducibility of blowing the fuse in this manner and the reliability of the fuse element once blown are all strongly dependent on the material covering the fuse.
In a conventional integrated circuit, the levels of metal that form the interconnect layers are each embedded in some form of deposited silicon dioxide to guarantee good electrical isolation between the conductors. The upper-most insulating layer, on top of the upper-most metal layer in the integrated circuit, also serves as a “passivation” layer. The passivation layer acts to protect the delicate integrated circuit from both mechanical damage and from the entry of foreign material (such as moisture or ionic contaminants) that might compromise the long-term reliability of the circuit. More commonly, the passivation layer on modern integrated circuits consists of a nitride layer deposited on the oxide layer in the circuit. The nitride layer is used because of its mechanical strength and its impermeability to moisture and ionic contaminants.
In an example prior art process, a semiconductor device is formed on a wafer substrate beginning with an insulating layer being deposited thereon. This insulating layer is typically silicon dioxide, however, other insulators may also be used. Examples of insulating materials include silicon dioxide, silicon oxynitride, silicon oxyfluoride, silicon nitride, other oxides and nitrides, amorphous carbon, spin-on glasses (such as silicates, siloxanes, hydrogen silsesquioxane, and alkyl silsesquioxanes), polymers (such as polyimides and fluoropolymers), and other nonconductive materials.
Photolithography and etching processes are often used to form a fuse layer along with other conductive interconnects (e.g., component-to-component connection within the IC). Such conductive materials may include doped polysilicon or metal alloys of aluminum, copper, or others. The geometry of the fuse or fusible element is not limited to any particular form; instead the form is governed by the needs of the process and the application. Chip designers are able to design varying-valued resistor structures by patterning layers in a variety of different shapes designed to fit well within a particular design layout. By way of example, the resistance “R” of a patterned shape is determined by multiplying the ratio of (“length”/“width”) by the resistivity expressed in terms of sheet resistance.
For the design of reliable and reproducible fuses, the top passivation layer of the integrated circuit is often a major consideration. For fuse optimization, avoiding use of a nitride film on top of the conductive film of the fuse is advantageous because the mechanical robustness of the nitride film tends to resist the vaporization of the fuse material, making it hard to blow the fuse. If sufficient energy is coupled into the fuse to overcome this resistance, the vaporization of the fuse is more explosive, and may tend to damage nearby circuit elements. For this reason, it is usually preferable to remove the nitride layer in the immediate region over the fuse. Some implementations choose to remove the nitride layer, but leave a layer of silicon dioxide on top of the fuse to improve the integrity of the protective seal on top of the integrated circuit. Because the majority of the fuses in any memory will not be blown, it is desirable that they remain covered with a protective layer of oxide in order to provide a degree of mechanical and chemical protection.
Another reason for leaving some of the silicon dioxide relates to the reliability of fuse blowing. If there is no encapsulating layer on top of the fuse trying to contain the vaporized metal, the fuse can be melted and blown with a relatively small amount of laser energy. If the fuse is blown in this way, the vaporized metal may not be forcibly expelled and may be redeposited in the vicinity of the remaining fuse body. Over time, this type of structure may tend to become more conductive and pose a reliability risk to the functionality of the circuit. There is a need to develop a fuse link that can be opened with precision and reliability and that can be formed using conventional manufacturing processes.
SUMMARY OF THE INVENTION
The present invention is directed to the formation of an insulative layer over a fuse link in a semiconductor device, with the insulative layer being sufficiently thick to encapsulate the fuse body during laser opening and prevent vaporized metal from re-depositing on the fuse body. The insulative layer is also sufficiently thin to allow the laser to penetrate the insulative layer during laser opening of the fuse. The present invention also provides a method of removing an ILD (interlayer dielectric) over the fuse with some precision by first forming the oxide layer over the fuse with a necessary thickness, in relation to the wavelength of the laser light beam used in the manufacturing process, before the other layers of the ILD are formed. This advantageously permits for selective etching to remove the upper layers of the ILD until the oxide layer above the fuse is exposed. Further etching is not required since the thickness of the oxide layer above the fuse link was determined at the onset.
Haley Mark W.
Mitchell Todd
Koninklijke Philips Electronics
Wilson Christian D.
Zarabian Amir
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