Backend interconnect scheme with middle dielectric layer...

Details Backend interconnect scheme with middle dielectric layer... Backend interconnect scheme with middle dielectric layer...

2011-05-03

2011-05-03

Dang, Phuc T (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

Reexamination Certificate

active

07936067

ABSTRACT:
An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.

REFERENCES:
patent: 7592710 (2009-09-01), Hsia et al.
patent: 2003/0218259 (2003-11-01), Chesire et al.
patent: 2004/0251549 (2004-12-01), Huang et al.
patent: 2007/0120256 (2007-05-01), Chen

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