Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2005-03-22
2005-03-22
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S401000, C257S797000
Reexamination Certificate
active
06869861
ABSTRACT:
A wafer includes a vertical scribe line and a horizontal scribe line on a front-side surface of the wafer. An intersection of the vertical scribe line and the horizontal scribe line is optically recognized through a wafer support attached to the front-side surface of the wafer. The wafer is drilled all the way through at the intersection to form a back-side alignment mark on a back-side surface of said wafer. The back-side alignment mark is used to aligning a saw, which singulates the wafer from the back-side surface.
REFERENCES:
patent: 5362681 (1994-11-01), Roberts, Jr. et al.
patent: 5777392 (1998-07-01), Fujii
patent: 5888884 (1999-03-01), Wojnarowski
patent: 6071656 (2000-06-01), Lin
patent: 6102775 (2000-08-01), Ushio et al.
patent: 6132910 (2000-10-01), Kojima
patent: 6151120 (2000-11-01), Matsumoto et al.
patent: 6151344 (2000-11-01), Kiely et al.
patent: 6275277 (2001-08-01), Walker et al.
patent: 6316334 (2001-11-01), Sivilotti et al.
patent: 6340547 (2002-01-01), Chen et al.
patent: 6407360 (2002-06-01), Choo et al.
patent: 6420776 (2002-07-01), Glenn et al.
patent: 6421456 (2002-07-01), Son et al.
patent: 6476415 (2002-11-01), Walker et al.
patent: 6492189 (2002-12-01), Yamaguchi
patent: 6528393 (2003-03-01), Tao
patent: 6537836 (2003-03-01), Summerer
patent: 20020031899 (2002-03-01), Manor
patent: 20030054588 (2003-03-01), Patel et al.
patent: 60-42846 (1985-03-01), None
patent: 7273069 (1995-10-01), None
patent: 2003188263 (2003-07-01), None
Glenn Thomas P.
Hollaway Roy Dale
Webster Steven
Amkor Technology Inc.
Fourson George
Gunnison McKay & Hodgson, L.L.P.
Hodgson Serge J.
Maldonado Julio J.
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