Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2008-07-22
2010-12-14
Smith, Bradley K (Department: 2894)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S261000, C257S314000, C438S197000, C365S185010
Reexamination Certificate
active
07851827
ABSTRACT:
Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention and reduces the possibility of damage to the channel/insulator interface. The direct tunneling program and efficient erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory device embodiments of the present invention are presented that are arranged in NOR or NAND memory architecture arrays. Memory cell embodiments of the present invention also allow multiple levels of bit storage in a single memory cell, and allow for programming and erase with reduced voltages.
REFERENCES:
patent: 4776922 (1988-10-01), Bhattacharyya et al.
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5751037 (1998-05-01), Aozasa et al.
patent: 5886368 (1999-03-01), Forbes et al.
patent: 6054734 (2000-04-01), Aozasa et al.
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6534816 (2003-03-01), Caywood
patent: 6586797 (2003-07-01), Forbes et al.
patent: 6664589 (2003-12-01), Forbes et al.
patent: 6713810 (2004-03-01), Bhattacharyya
patent: 6743681 (2004-06-01), Bhattacharyya
patent: 6754108 (2004-06-01), Forbes
patent: 6759712 (2004-07-01), Bhattacharyya
patent: 6768156 (2004-07-01), Bhattacharyya
patent: 6778441 (2004-08-01), Forbes et al.
patent: 6784480 (2004-08-01), Bhattacharyya
patent: 6849464 (2005-02-01), Drewes
patent: 6864139 (2005-03-01), Forbes
patent: 6900455 (2005-05-01), Drewes
patent: 6903969 (2005-06-01), Bhattacharyya
patent: 6917078 (2005-07-01), Bhattacharyya
patent: 6933572 (2005-08-01), Bhattacharyya
patent: 2002/0076850 (2002-06-01), Sadd et al.
patent: 2002/0140023 (2002-10-01), Ohba et al.
patent: 2003/0001232 (2003-01-01), Koinuma et al.
patent: 2003/0033573 (2003-02-01), Tamura et al.
patent: 2003/0042527 (2003-03-01), Forbes et al.
patent: 2003/0042532 (2003-03-01), Forbes
patent: 2003/0042534 (2003-03-01), Bhattacharyya
patent: 2003/0043632 (2003-03-01), Forbes
patent: 2003/0043633 (2003-03-01), Forbes et al.
patent: 2003/0043637 (2003-03-01), Forbes et al.
patent: 2003/0045082 (2003-03-01), Eldridge et al.
patent: 2003/0048666 (2003-03-01), Eldridge et al.
patent: 2003/0089942 (2003-05-01), Bhattacharyya
patent: 2003/0151948 (2003-08-01), Bhattacharyya
patent: 2004/0041206 (2004-03-01), Bhattacharyya
patent: 2004/0123085 (2004-06-01), Oikawa et al.
patent: 2004/0183122 (2004-09-01), Mine et al.
patent: 2005/0167734 (2005-08-01), She et al.
patent: 2006/0261401 (2006-11-01), Bhattacharyya
patent: 2007/0012988 (2007-01-01), Bhattacharyya
patent: 2152225 (1972-05-01), None
M. Kwan Cho et al., High Performance SONOS Memory Cells Free of Drain Turn-On and Over-Erase: Compatibility Issue with Current Flash Technology, IEEE Electron Device Letters, Vol. 21, No. 8, Aug. 2000, pp. 399-401.
F. Ito et al., A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embeded Nonvolatile Memory Applications, VLSI Technology Digest of Technical Papers, 2004, pp. 80-81.
M. Fukuda et al., Scaled 2 bit/cell SONOS Type Nonvolatile Memory Technology for sub-90nm Embedded Application using SiN Sidewall Trapping Structure, IEDM, 2003, pp. 37.5.1-37.5.4.
C.C. Yeh et al., Novel Operation Schemes to Improve Device Reliability in a Localized Trapping Storage SONOS-type Flash Memory, IEDM, 2003, pp. 7.5.1-7.5.4.
K.W. Guarini et al., Low voltage scalable nanocrystal FLASH memory fabricated by templated self assembly, IEDM, 2003, pp. 22.2.1-22.2.4.
S.J. Baik et al., High Speed and Nonvolatile Si Nanocrystal Memory for Scaled Flash Technology using Highly Field-Sensitive Tunnel Barrier, IEDM, 2003, pp. 22.3.1-22.3.4.
H. Silva et al., Few Electron Memories: Finding the Compromise between Performance, Variability and Manufacturability at the Nano-Scale, IEDM, 2003, pp. 10.5.1-10.5.4.
R. Ranica et al., A new 40nm SONos structure based on backside trapping for nanoscale memories, VLSF, 2004, pp. 99-100.
C. Lee et al., A Novel SONOS Structure of SiO2/SiN/Al203with TaN metal gate for multi-giga bit flash memeries, 2003, IEDM, pp. 26.5.1-26.5.4.
P. Blomme et al., Data retention of floating gate Flash memory with SiO2/high-k tunnel or interpoly dielectric stack, 2004, Infineon Technologies.
J. Buckley et al., Engineering of “Conduction Band-Crested Barriers” or “Dielectric Constant Crested Barriers” in view of their application to floating-gate non-volatile memory devices, 2004, VKSU, pp. 55-56.
C. Lee et al., Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single-and Double-Layer Metal Nanocrystals, 2003, IEDM, pp. 22.6.1-22.6.4.
M. Takata et al., New Non-volatile Memory with Extremely High Density Metal Nano-Dots, 2003, IEDM, pp. 22.5.1-22.5.4.
Cheng-Yuan Hsu et al.;Split-Gate NAND Flash Memory at 120nm Technology Node Featuring Fast Programming and Erase; 2004; 2004 Symposium on VLSI Technology Digest of Technical Papers; pp. 78-79.
D. Lee et al.;Vertical floating-gate 4.5F2Split-gate NOR Flash Memory at 110nm Node; 2004; 2004 Symposium on VLSI Technology Digest of Technical Papers; pp. 72-73.
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
Smith Bradley K
Valentine Jami M
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