Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-09
2001-08-28
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S365000, C257S366000
Reexamination Certificate
active
06281551
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a silicon structure and to a method of making the silicon structure, and more particularly to small complementary metal oxide semiconductor (CMOS) circuitry and a method of producing the small CMOS circuitry such as transistors, memories, etc. and integration of the same using a common substrate structure.
2. Description of the Related Art
Bonding of silicon dioxide and silicon has been practiced for many years. Several manufacturers supply wafers in which, in a desired step, two substrates are bonded together with silicon dioxide as the bonding layers.
For example, Lasky, “Wafer Bonding for Silicon-On-Insulator Technologies”
Appl. Phs. Lett
. 48 78(1986), described this procedure originally. Aspar et al., “Basic Mechanisms Involved in the Smart-Cut Process,”
Microelectronic Engineering
36 233(1997), describe the smart-cut process where a bonded wafer breaks off due to excess hydrogen. Sanchez et al., “Spontaneous Direct Bonding of Thick Silicon Nitride,”
J. Micromech. Microeng
. 7 111 (1997), describe bonding with silicon nitride. Tong et al., “Silicon Carbide Wafer Bonding,”
J. Electrochem. Soc
, 142 232(1995), describe bonding with silicon carbide. Goh et al., “Electrical Characterization of Dielectrically Isolated Silicon Substrates Containing Buried Metallic Layer,”
IEEE Electron Device Letters
18 232 (1997), describe use of WSi
2
by using a poly-silicon capping of tungsten to bond to a silicon dioxide layer.
A problem of conventional techniques and structures is that, at small gate lengths, it becomes increasingly difficult to control the flow of electrons by the gate and independent of the drain voltage. Specifically, control of current close to the gated oxide/semiconductor interface is an increasingly difficult problem as gate lengths are reduced. Achieving good control requires an electrostatic potential barrier from the channel towards the substrate.
Such a potential barrier is typically produced by doping. However, such a procedure becomes difficult at small dimensions. Specifically, this higher doping in the substrate suffers from problems of random dopant distribution and control in placing of dopants.
Another method is to provide a back-plane which is separated from the conducting silicon by a barrier of an insulator. A back-plane of thick silicon with thick oxide is described by I. C. Yang et al., “Back-gated CMOS on FOIAS for Dynamic Threshold Voltage Control”,
Tech. Digest of IEDM
, 1995. However, the conventional methods of providing a back-plane for such a purpose have been problematic. For example, the insulators are thick, the backplane silicon is thick, and the method of formation leaves hydrogen in the insulator which leads to memory effects following a high temperature anneal. Further, large voltages are required.
SUMMARY OF THE INVENTION
In view of the foregoing problems of the conventional structures, it is therefore an object of the present invention to provide a method of making an inert conductive layer underneath a thin silicon layer separated by a silicon dioxide or other dielectric layer.
A second object of the invention is to provide a method for attaching an insulator layer to a metal in atomically intimate contact and with a negligible interface reaction.
Another object of the invention is to provide a conducting layer underneath the thin silicon layer that does not interfere with semiconductor manufacturing processes, is not contaminating, and can withstand processing temperatures and etching, deposition, and oxidation conditions.
Yet another object is to produce a wafer structure that will allow for newer forms of device structures to become feasible.
In a first aspect of the present invention, a method of forming a semiconductor structure, includes steps of: growing a thin oxide layer on a silicon-on-insulator (SOI) substrate to form a first wafer; separately forming a smooth metal film on an oxidized silicon substrate to form a second wafer; aligning the first and second wafers with respect to one another for attachment, thereby attaching the first wafer to the second wafer (e.g., by van der Waals' forces); performing a heat cycle for the first and second wafers, in a nitrogen ambient, to form a bond between the first and second wafers; and detaching the substrate of the first wafer from the bonded first and second wafers. Preferably, before the aligning step, at least one of a surface of the first wafer and a surface of the second wafer is hydrogentreated.
In a second aspect of the present invention, a method of forming a back-plane for a semiconductor device, includes steps of: growing an oxide layer on a first substrate to form a first wafer; separately forming a metal film on an oxidized second substrate to form a second wafer; dipping the first and second wafers in an acid mixture; aligning the first and second wafers with respect to one another for attachment; performing a heat cycle to form a bond between the first and second wafers; and detaching a portion of the first wafer from the second wafer, to form a wafer structure.
Preferably, the refractory metal includes tungsten.
In a third aspect of the present invention, a method of forming a back-plane, includes steps of: forming a first wafer including a silicon-on-insulator (SOI) structure; bonding the first wafer to a second wafer, the second wafer including a refractory metal-coated substrate; and removing the first wafer from the second wafer, thereby forming a backplane for a semiconductor device.
With the unique and unobvious features of the present invention, a method is provided for producing back-planes which allow for an electrostatic potential barrier by a back-bias, and produces substrates with such back-planes.
In an exemplary embodiment, the present invention provides bonding at an 8-inch wafer scale with a back-plane of, for example, tungsten. Tungsten is shown to maintain its interface acuity through high temperature bonding. This allows back-plane transistors and other structures to be fabricated easily, reliably, and with excellent performance characteristics.
Additionally, present microelectronics fabrication methods can continue to be used on these substrates to form devices with superior characteristics and also allows for different forms of devices.
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Sze, Semiconductor devices Physics and Technology, p. 355, copyright 1985.
Chan Kevin Kok
D'Emic Christopher Peter
Jones Erin Catherine
Solomon Paul Michael
Tiwari Sandip
August Casey P.
International Business Machines - Corporation
McGinn & Gibb PLLC
Ngo Ngan V.
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