Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2010-01-08
2011-10-04
Dang, Trung Q (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S458000, C257SE21421
Reexamination Certificate
active
08030145
ABSTRACT:
A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.
REFERENCES:
patent: 5289027 (1994-02-01), Terrill et al.
patent: 5619054 (1997-04-01), Hashimoto
patent: 5942781 (1999-08-01), Burr et al.
patent: 6072217 (2000-06-01), Burr
patent: 6080610 (2000-06-01), Hashimoto
patent: 6100567 (2000-08-01), Burr
patent: 6307233 (2001-10-01), Awaka et al.
patent: 6335214 (2002-01-01), Fung
patent: 6383904 (2002-05-01), Yu
patent: 6391695 (2002-05-01), Yu
patent: 6423599 (2002-07-01), Yu
patent: 6611023 (2003-08-01), En et al.
patent: 2010/0176482 (2010-07-01), Dennard et al.
patent: 2011/0114918 (2011-05-01), Lin et al.
patent: 05267663 (1993-10-01), None
Young, K. K., “Short-Channel Effect in Fully-Depleted SOI MOSFETs” IEEE Trans. Electron Devices (1989) pp. 399-402, vol. 36.
Trivedi, V. P. et al., “Scaling Fully Depleted SOI CMOS” IEEE Trans. Electron Devices (2003) pp. 2095-2103, vol. 50.
Kumar, A. et al., “Quantum-Based Simulation Analysis of Scaling in Ultrathin Body Device Structures” IEEE Trans. Electron Devices (2005) pp. 614-617, vol. 52.
Singh, D. V. et al., “Stress Memorization in High-Performance FDSOI Devices with Ultra-Thin Silicon Channels and 25 nm Gate Lengths” IEDM Tech. Dig. (2005) pp. 511-514.
Trivedi, V. P. et al., “Nanoscale FDSOI CMOS: Thick or Thin BOX?” IEEETrans. Electron Device Letter (2005) pp. 26-28, vol. 26.
Chang Leland
Ji Brian L.
Kumar Arvind
Majumdar Amlan
Saenger Katherine
Dang Trung Q
International Business Machines - Corporation
Percello, Esq. Louis J.
Scully , Scott, Murphy & Presser, P.C.
LandOfFree
Back-gated fully depleted SOI transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Back-gated fully depleted SOI transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Back-gated fully depleted SOI transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4290808