Back-gate controlled read SRAM cell

Details Back-gate controlled read SRAM cell Back-gate controlled read SRAM cell

2007-02-13

2007-02-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S230010, C365S185010

Reexamination Certificate

active

11100893

ABSTRACT:
An eight transistor static random access memory (SRAM)device includes first and second inverters, a first bit line, a first complement bit line, a pair of write access transistors, and a pair of read access transistors. Each of the first and second inverters includes a respective pair of transistors, and has a respective data node. Each of a first and a second of the access transistors has a source, a drain, a front gate, and a back gate. The first access transistor is coupled to the first bit line, and the second access transistor is coupled to the first complement bit line. The back gate of the first access transistor is coupled to the data node of the first inverter; and the back gate of the second access transistor is coupled to the data node of the second inverter. This increases the difference between the threshold voltages of the first and second access transistors.

REFERENCES:
patent: 6078544 (2000-06-01), Park
patent: 6576962 (2003-06-01), Rockett
patent: 6654277 (2003-11-01), Hsu et al.
patent: 6816401 (2004-11-01), Kauffmann et al.
patent: 2002/0006072 (2002-01-01), Kunikiyo
patent: 2005/0169054 (2005-08-01), Forbes

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