Back-gate controlled asymmetrical memory cell and memory...

Details Back-gate controlled asymmetrical memory cell and memory... Back-gate controlled asymmetrical memory cell and memory...

2007-12-25

2007-12-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S155000, C365S156000, C365S203000

Reexamination Certificate

active

11362613

ABSTRACT:
Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

REFERENCES:
patent: 5673230 (1997-09-01), Kuriyama
patent: 5986924 (1999-11-01), Yamada
patent: 6198656 (2001-03-01), Zhang
patent: 6573549 (2003-06-01), Deng et al.
patent: 6831483 (2004-12-01), Shimazaki et al.
patent: 7177177 (2007-02-01), Chuang et al.
patent: 7200030 (2007-04-01), Yamaoka et al.
Chuang et al., “Independent-Gate Controlled Asymmetrical Memory Cell and Memory Using the Cell,” U.S. Appl. No. 11/362,612, filed Feb. 27, 2006.
Chuang et al., “Asymmetrical Memory Cells and Memories Using the Cells,” U.S. Appl. No. 11/392,071, filed Mar. 29, 2006.
Kuriyama et al., “An Asymmetric Memory Cell using a C-TFT for ULSO SRAMs,” Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39 (1992).
Itabashi et al., “A Split Wordline Cell for 16Mb SRAM Using Polysilicon Sidewall Contacts,” IEEE, IEDM 91 (1991).
“Taurus-Medici: Industry-standard device simulation tool,” Synopsys Data Sheet (2003).
Shang et al., “Mobility and CMOS Devices/Circuits on sub-10nm (110) Ultra Thin Body SOI,” Symposium on VLSI Technology Digest of Technical Papers, pp. 78-79 (2005).
Kim et al., “Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS,” Solid-State Electronics 48, pp. 239-243 (2004).
Takeda et al., “A Read-Static-Noise-Margin-Free SRAM Cell for Low-Vddand High-Speed Applications,” IEEE International Solid-State Circuits Conference, pp. 478-479, 611 (2005).
Azizi et al., “Low-Leakage Asymmetric-Cell SRAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 4, pp. 701-715 (Aug. 2003).
Guo et al., “FinFET-Based SRAM Design,” ISLPED (Aug. 8-10, 2005).
Yamaoka et al., “Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 288-291 (2004).

Affiliated with

Also associated with

Rating

Back-gate controlled asymmetrical memory cell and memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Back-gate controlled asymmetrical memory cell and memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Back-gate controlled asymmetrical memory cell and memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3870331