Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1995-10-16
1998-05-19
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257345, 257386, 257391, 257402, 257403, 257404, H01L 2976, H01L 2994, H01L 31113, H01L 31062
Patent
active
057539588
ABSTRACT:
An adjustable threshold voltage MOS device having an asymmetric pocket region is disclosed herein. The pocket region abuts one of a source or drain proximate the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. An MOS device having such pocket region may have its threshold voltage adjusted by applying a potential directly to its pocket region. This capability is realized by providing a contact or conductive tie electrically coupled to the pocket region. This "pocket tie" is also electrically coupled to a metallization line (external to the device) which can be held at a specified potential corresponding to a potential required to back-bias the device by a specified amount.
REFERENCES:
patent: 4300150 (1981-11-01), Colak
patent: 4939571 (1990-07-01), Nishizawa et al.
patent: 4949140 (1990-08-01), Tam
patent: 5304827 (1994-04-01), Malhi et al.
patent: 5386136 (1995-01-01), Williams et al.
Yan, R. H.; Lee, K. F.; Jeon, D. Y.; Kim, Y. O.; Park, B. G.; Pinto, M. R.; Rafferty, C. S.; Tennant, D. M.; Westerwick, E. H.; Chin, G. M.; Morris, M.D.; Early, K.; Mulgrew, P.; Mansfield, W. M.; Watts, R. K.; Voshchenkov, A. M.; Bokor, J.; Swartz, R. G.; and Ourmazd, A.; "High Performance 0.1-.mu.m Room Temperature Si MOSFETs", Symposium on VLSI Technology Digest of Technical Papers, pp. 86-87, 1992.
Aoki, M.; Ishii, T.; Yoshimura, T.; Iiiyima, S., Yamanaka, T.; Kure, T.; Ohyu, K.; Shimohigashi, K.; "0.1 .mu.m CMOS Devices Using Low-Impurity Channel Transistors (LICT)", pp. 9.8.1 - 9.8.3, IEDM, 1987.
Yoshimura, Hisao; Matsuoka, Fumitomo; and Masakaru, Kakumu "New CMOS Shallow Junction Well FET Structure (CMOS-SJET) for Low Power-Supply Voltage", Semiconductor Device Engineering Laboratory, Japan, Proceedings of IEDM (1992), pp. 909-912.
Burr, Jim; "Stanford Ultra Low Power CM0S Technology", NASA VLSI Design Symposium, pp. 4.2.1-4.2.13, 1991..
Burr, Jim; "Stanford Ultra Low Power CMOS", Symposium Record, Hot Chips. V, pp. 7.4.1-7.4.12, Stanford, CA, 1993.
Burr, James B, and Peterson, Allen M.; "Energy Considerations in Multichip-Module Multiprocessors", IEEE International Conference on Computer Design,pp. 593-600. 1991.
"A New Lease on Life for Old-Fashioned Chips", Business Week, Science and Technology, p. 100, Dec. 20, 1993.
Burr, James B., and Scott, John, "A 200m V Self-Testing Encoder/Decoder using Stanford Ultra-Low Power CMOS", IEEE International Solid-State Circuits Conference, 1994.
Notes from Dr. Burr's dinner meeting with Hitachi employee.
Okumura, Yoshinori; Shirahata, Masayoshi; Hachisuka, Atsushi; Okudaira, Tomonori; Arima, Hideaki; and Matsukawa, Takayuki; "Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability", pp. 2541-2552, IEEE Transaction on Electron Devices, vol. 39, No. 11, Nov. 1992.
Sai-Halasz, George A.; Wordeman, Matthew R.; Kern, D.P.; Rishton, S.; and Ganin, E. "High Transconductance and Velocity Overshoot in NMOS Devices at the 0.1 .mu.m Gate-Length Level", pp. 464-466, IEEE Electron Device Letters, vol. 9, No. 9, Sep. 1988.
Jayaraman, R.; Rumennik, V.; Singer, B. and Stupp, E.H., "Comparison of High Voltage Devices for Power Integrated Circuits," pp. 258-261, CH2099-0/84/0000-0258, IEDM 1984.
Tanaka, Junko; Kimura, Shin'ichiro, Noda, Hiromasa, Toyabe, Toru, and Ihara, Sigeo, "A Sub-0.1-.mu.m Grooved Gate MOSFET with High Immunity to Short-Channel Effects," pp. 537-540, IEEE Transaction on Electionic Device, vol. 42, No. 3, Mar. 1995.
Huang, Wen-Ling Margaret, Klein, Kevin M., Grimaldi, M., Racanelli, Marco, Ramaswami, Shri, Taso, J., Foerstner, Juergen, and Hwang, Bor-Yuan C., Member IEEE, "TFSOI Complementary BiCMOS Technology for Low Power Applications," pp. 506-512, IEEE Transaction on Electronic Devices, vol. 42, No. 3, March 1995.
Burr James B.
Laird Douglas Alan
Ngo Ngan V.
Sun Microsystems Inc.
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