Back bias generator having transfer transistor with well bias

Details Back bias generator having transfer transistor with well bias Back bias generator having transfer transistor with well bias

1998-06-24

2001-01-16

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S534000

Reexamination Certificate

active

06175263

ABSTRACT:

This application corresponds to Korean patent application No. 97-27609 filed Jun. 26, 1997 in the name of Samsung Electronics Co., Ltd., which is herein incorporated by reference for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to a method and apparatus for reducing leakage current in a transfer transistor in a back bias voltage generator for a DRAM semiconductor device.
2. Description of the Related Art
A DRAM semiconductor device has a plurality of memory cells for storing information and peripheral circuits for reading and writing data to the memory cells. During operation of a DRAM semiconductor device, leakage current can be generated between the memory cells, the peripheral circuits, and the substrate of the DRAM device. To prevent leakage current, a back bias generator is used to apply a back bias to the substrate.
FIG. 1
is a circuit diagram of a conventional back bias generator for a DRAM semiconductor device. Referring to
FIG. 1
, the conventional back bias generator
5
includes an oscillator
11
, a power-supply voltage generator
13
, a NAND gate
15
, a pumping capacitor (Cp), a clamp transistor
17
and a PMOS transfer transistor
19
.
The operation of the back bias generator for a semiconductor device
5
will now be explained. When the power-supply voltage generator
13
begins generating a power-supply voltage Vcc, the oscillator
11
generates a clock signal. In response to the clock signal, the pumping capacitor Cp generates a negative pumping voltage. The negative pumping voltage is generated as a back bias V
BB
through the transfer transistor
19
.
FIG. 2
is a sectional view of a DRAM semiconductor device
7
showing the structure of transfer transistor
19
. Referring to
FIG. 2
, an N well
23
is formed in a P-substrate
21
. A source
25
and a drain
27
for the transfer transistor
19
are formed in the N well
23
.
As DRAM memory cells become more highly integrated, the design rule is reduced and the level of a power-supply voltage Vcc is lowered. Accordingly, the power-supply capacity of a back bias generator becomes insufficient. Therefore, to improve the power supply capacity of the back bias generator for a semiconductor device, the PMOS transistor used as the transfer transistor shown in
FIG. 1
must be replaced with an NMOS transistor. This is because an NMOS transistor has a threshold voltage that is lower than that of a PMOS transistor while having a greater driving capacity.
FIG. 3
is a circuit diagram of a conventional back bias generator
35
that utilizes an NMOS transistor as a transfer transistor
39
. The power supply capacity of the back bias generator
35
of
FIG. 3
is greater than that of the circuit of FIG.
1
. However, when the circuit shown in
FIG. 3
is utilized in a DRAM semiconductor device having a triple-well structure, as shown in
FIG. 4
, a leakage current il is generated between the transfer transistor
39
and the P-substrate
21
because a PNP structure
43
is formed between the transfer transistor
39
and the P-substrate
21
. Reference numeral
30
designates the gate of transfer transistor
39
.
Referring to
FIGS. 3 and 4
, the negative pumping voltage generated by the pumping capacitor Cp does not pass through the transfer transistor
39
but is discharged to the P-substrate
21
through the PNP structure
43
. This reduces the power supply capacity of the back bias generator
35
shown in FIG.
3
. Accordingly, leakage current is generated between memory cells (not shown) that utilize the back bias V
BB
. This phenomenon is serious at power-up time. The leakage current deteriorates the refresh characteristics of the DRAM semiconductor device. Also, instability of the back bias level due to noise in the DRAM reduces the response time of the device.
Accordingly, a need remains for an improved scheme for generating a back bias signal in a semiconductor device.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to improve the refresh characteristics of a DRAM semiconductor device.
Another object of the present invention is to reduce leakage current in a DRAM semiconductor device.
A further object of the present invention is to improve the back bias supply capacity of a back bias generator for a semiconductor device.
To accomplish these and other objects, a back bias generator for a semiconductor device constructed in accordance with the present invention applies a well bias voltage to the bulk of an NMOS transfer transistor formed in a triple well structure. The back bias generator includes a well bias generator that generates the well bias voltage before the pumping voltage is applied to the transfer transistor. The well bias provides a back bias to a parasitic NPN transistor formed in the triple well of the NMOS transfer transistor, thereby preventing leakage through the NPN into the substrate. The well bias is also applied to the bulk of a clamp transistor that initializes a pumping capacitor.
One aspect of the present invention is a back bias generator for a semiconductor device having a triple well structure, comprising: an oscillator for generating a clock signal; a well bias generator coupled to the oscillator for generating a well bias signal in response to the clock signal; a power-supply voltage generator for generating a power-supply voltage; a logic gate coupled to the power-supply voltage generator and the oscillator for generating a logic signal responsive to the power supply voltage and the clock signal; a pumping capacitor coupled between the logic gate and a node for generating a pumping voltage at the node in response to the logic signal; and a transfer transistor having a first electrode coupled to the node, a bulk coupled to the well bias generator to receive the well bias signal, and a gate and second electrode coupled together, for generating a back bias signal at the second electrode. In a preferred embodiment, the voltage of the well bias signal is lower then the voltage of the back bias signal after the power-supply voltage reaches a predetermined level.
Another aspect of the present invention is a back bias generator for a semiconductor device having a triple well structure comprising: logic means for generating a logic signal that is at a first logic state if a power supply signal is below a predetermined level, a second logic state if a clock signal is at a third logic state, and the first logic state if the power supply signal is above the predetermined level and the clock signal is at a fourth logic state; a pumping capacitor coupled to the logic means, the pumping capacitor generating a pumping signal responsive to the logic signal; a transfer transistor coupled to the capacitor for receiving the pumping signal and generating a back bias signal; and bias means for generating a well bias signal coupled to the transfer transistor for providing a well bias signal to a bulk of the transfer transistor, thereby preventing leakage through the triple well structure. In a preferred embodiment the back bias generator further includes a clamp transistor coupled to the pumping capacitor for initializing the voltage of the pumping capacitor, the clamp transistor having a bulk coupled to the bias means for receiving the well bias signal. The bias means provides the well bias signal before the logic means causes the pumping capacitor to generate the pumping signal.
A further aspect of the present invention is a method for operating a back bias generator having a transfer transistor fabricated in a triple well structure, wherein a first well of the triple well structure forms the bulk of the transfer transistor, the method comprising: generating a pumping signal; applying the pumping signal to a first terminal of the transfer transistor; generating a well bias signal; and applying the well bias signal to the bulk of the transfer transistor, thereby preventing leakage through the triple well structure.
An advantage of the present invention is that it reduces l

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