Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Patent
1998-04-30
2000-07-11
Pan, Daniel H.
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
712206, 712223, 712245, 712209, G06F 930, G06F 9312, G06F 9318, G06F 938
Patent
active
060887923
ABSTRACT:
A computer processor that allows the execution of the IBM ESA/390 SPKA instruction, in an overlapped fashion, contains an apparatus that allows the SPKA instruction to be executed without serializing the processor after its execution in most cases, thereby improving performance. It contains a mechanism in the processor's cache that monitors if the Fetch Protect bit in the storage key is on, for instruction data being fetched. It also contains a mechanism to remember if an SPKA instruction has been executed recently. Based on this information, an apparatus determines if it really must serialize the processor after execution of the SPKA instruction.
REFERENCES:
patent: 4891749 (1990-01-01), Hoffman et al.
patent: 5060148 (1991-10-01), Isobe et al.
patent: 5257354 (1993-10-01), Comfort et al.
patent: 5307483 (1994-04-01), Knipfer et al.
patent: 5345567 (1994-09-01), Hayden et al.
patent: 5440703 (1995-08-01), Ray et al.
patent: 5748951 (1998-05-01), Webb et al.
patent: 5941997 (1999-08-01), Greaves
patent: 5949971 (1999-09-01), Levine et al.
"The Effects of MP Serialization on Logical Partitioning Capacity" by Bob Ellsworth, Amdahl Corporation, pp. 399-407.
"Maintaining Application Compatibility in Multiprocessor Environments" IBM Technical Disclosure Bulletin, vol. 38, No. 8, Aug. 1995, pp. 333-334.
Special Serialization for "Load-with-Update" Instruction to Reduce the Complexity of Register Renaming Circuitry IBM Technical Disclosure Bulletin, vol. 37, No. 10, Oct. 1994, pp. 59-60.
"PowerPC 601/604 Multiprocessor Random Verification Methodology" IBM Technical Disclosure Bulletin, vol. 37, No. 10, Oct. 1994, pp. 557-561.
"Designing Flexibility into Hardwired Logic" IBM Technical Disclosure Bulletin, vol. 37, No. 3, Mar. 1994, pp. 321-324.
"Multisequencing in a Single Instruction Stream Processing of Parallel Streams" IBM Technical Disclosure Bulletin, vol. 37, No. 1, Jan. 1994, pp. 133-139.
"Offloading Synchronization at 2nd Level" IBM Technical Disclosure Bulletin, vol. 36, No. 7, Jul. 1993, pp. 471-474.
"Multisequencing a Single Instruction Stream--Meta High-End Machine Eliminating SLIST and DLIST" IBM Technical Disclosure Bulletin, vol. 36, No. 6A, Jun. 1993, pp. 91-94.
MSIS Handling S/370 Serialization in MSIS Without Delay, IBM Technical Disclosure Bulletin, vol. 36, No. 1, Jan. 1993, pp. 466-469.
"MSIS MP Version" IBM Technical Disclosure Bulletin, vol. 36, No. 1, Jan. 1993, pp. 317-322.
"System Support for Multiprocessing without an Atomic Storage" IBM Technical Disclosure Bulletin, vol. 33, No. 9, Feb. 1991, pp. 18-23.
Slegel Timothy John
Webb Charles Franklin
Augspurger Lynn L.
Chang Jung-won
International Business Machines - Corporation
Pan Daniel H.
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