Avoiding mapping conflicts in a translation look-aside buffer

Details Avoiding mapping conflicts in a translation look-aside buffer Avoiding mapping conflicts in a translation look-aside buffer

2000-10-19

2003-05-20

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S203000, C711S216000, C711S220000

Reexamination Certificate

active

06567907

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to translation look-aside buffers in computer systems.
2. Art Background
A computer system typically includes a processor and a main memory. The main memory of a computer system usually stores instructions and data. A processor typically has a processor architecture which provides a virtual address space for referencing instructions and data. The main memory, on the other hand, usually has a memory architecture which provides a physical address space for storing instructions and data. Typically, the physical address space of a main memory is much smaller than the virtual address space of a processor. In addition, the physical address space of a main memory may have discontinuities in its ranges of valid addresses.
Computer systems commonly include address translation mechanisms for translating the virtual addresses used by a processor to the appropriate physical addresses for accessing a main memory. An address translation mechanism typically includes a page directory which is stored in main memory. A typical page directory includes a set of entries each of which contains a set of address translation information.
In addition, prior computer systems commonly include one or more translation look-aside buffers (TLBs). A typical TLB holds a subset of the translation information contained in the page directory. A typical TLB may be viewed as a cache of the page directory entries. TLBs usually enhance the speed of a processor by avoiding main memory accesses to the page directory during translation of virtual addresses to physical addresses.
It is usually desirable that a TLB be implemented using a relatively simple structure so that the TLB can be read in a single processor cycle or relatively few processor cycles, thereby enhancing processor performance. In addition, a TLB with a relatively simple structure usually reduces hardware costs associated with a computer system.
An example of relatively simple TLB structure is a direct-mapped structure in which a virtual address maps to its own particular TLB entry. Unfortunately, such direct mapping usually means that the address translation information for virtual addresses that map to the same TLB entry cannot be held in the TLB at the same time. Virtual addresses that map to the same TLB entry are said to have a mapping conflict. Such mapping conflicts in a TLB usually increase the miss rate to the TLB and slow overall performance in a computer system.
SUMMARY OF THE INVENTION
A computer system is disclosed with mechanisms for avoiding mapping conflicts in a translation look-aside buffer. A memory manager in the computer system allocates a virtual address to a process by determining a set of previously allocated virtual addresses for the process and then selecting the virtual address such that the mapping of the virtual address to the translation look-aside buffer does not conflict with any of the previously allocated virtual addresses.
Other features and advantages of the present invention will be apparent from the detailed description that follows.


REFERENCES:
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patent: 6079004 (2000-06-01), Liedtke
patent: 6418521 (2002-07-01), Mathews et al.
patent: 6430667 (2002-08-01), Loen

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