Avoiding deadlocks in a multiprocessor system

Details Avoiding deadlocks in a multiprocessor system Avoiding deadlocks in a multiprocessor system

2006-09-22

2009-10-06

Thai, Tuan V (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S119000, C711S128000, C711S135000, C711S141000, C711S147000, C711S148000

Reexamination Certificate

active

07600080

ABSTRACT:
In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a memory, directing the first memory request to a writeback queue of the home agent if the first memory request is a writeback request and otherwise directing the first memory request to a second queue of the home agent. In this way, circular dependencies may be avoided. Other embodiments are described and claimed.

REFERENCES:
patent: 6009488 (1999-12-01), Kavipurapu
patent: 6631448 (2003-10-01), Weber
patent: 6865634 (2005-03-01), McAllister
patent: 6938128 (2005-08-01), Kuskin et al.
patent: 2002/0116586 (2002-08-01), Tremblay et al.
patent: 2003/0217235 (2003-11-01), Rowlands
patent: 2004/0068620 (2004-04-01), Van Doren et al.
U.S. Appl. No. 11/474,140, filed Jun. 23, 2006, entitled, “Synchronizing Control and Data Paths Traversed by A Data Transaction” by Bipin P. Singh; Vivek Garg; Binata Bhattacharyya.

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