Avoiding cache collisions between frequently accessed, pinned ro

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711171, G06F 1208

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active

059604549

ABSTRACT:
The performance of a computer system having a faster memory unit and a slower memory unit is improved. Memory locations of the faster memory unit are shared by a plurality of memory locations of the slower memory unit. The frequently accessed routines and data structures in the system are identified. The size of each frequently accessed routine is determined. Each routine is associated with a Moment Value computed according to a size of each routine and a frequency of access of the routine. The Moment Values and the associated routines are sorted in descending order in a sorted Moment Value list so that the routine with the largest Moment Value is first in the sorted Moment Value list. The associated routines are arranged in the order of decreasing Moment Value at memory locations in the slower memory unit of the computer.
The performance of the program running on the computer system is improved by reducing contention for faster memory space among the frequently accessed routines.

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