Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1993-07-12
1995-09-19
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375374, 360 51, 327231, G11B 509, H03K 500, H03K 513, H03D 324
Patent
active
054523257
ABSTRACT:
A phase locked loop has an average zero phase start circuit to detect and correct for the average phase difference between a data signal and a VCO clock signal over a short interval at the beginning of phase-lock acquisition. The average zero phase start circuit has a data comparator to split the data stream into odd and even portions; odd and even pulse position detectors to detect the phase difference between pulses of the odd and even data signals and corresponding pulses of the VCO clock; and a ramp generator to generate a voltage corresponding to the sum of the detected phase differences. The ramp generator employs a capacitor and switched current sources that discharge the capacitor at a fixed rate to generate the voltage. After 4 phase difference measurements are taken, the VCO is stopped, and another current source discharges the capacitor at 4 times the fixed rate. A ramp comparator indicates when the capacitor voltage converges with a reference voltage to restart the VCO in the desired phase alignment with the data signal.
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Brown Russell W.
Doan Toai A.
Henderson Edward L.
Chin Stephen
Harrison David B.
May Timothy J.
Quantum Corp.
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