AV data input/output device

Details AV data input/output device AV data input/output device

1999-09-13

2002-09-10

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S035000, C709S203000, C711S113000

Reexamination Certificate

active

06449668

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an apparatus for storing, distributing or editing video data or audio data resulting from the digitization of video signals and audio signals.
BACKGROUND ART
There have been developed nonlinear editors (e.g. the Japanese Patent Application No. 8-176934) for editing pictures and sounds on a computer by connecting a recording/playback apparatus (VCR, video camera, hard disk or the like) via a dedicated interface or the bus of the computer and transferring data, as well as image servers for distributing video and audio data stored on a hard disk. Since such an apparatus involves the connection of a device which, such as a VCR, transfers data at a fixed rate and another which, such as a hard disk, transfers data at an unfixed rate, gives rise to a situation in which, in the event of a temporary delay in the transfer from the hard disk, some data are skipped. To solve this point, there is a method of outputting data while they are scheduled.
FIG. 15
is a configurational diagram of a conventional system using this method.
An HDD
7
in which video data-are stored is connected to the bus of a computer, e.g. a PCI bus
4
, via an SCSI Host Adapter (hereinafter SCSI HA)
6
. A CPU
1
and a main memory
2
are connected by a CPU bus and further connected to the PCI bus
4
via a bridge
5
. A data input/output circuit
100
comprises a decoder
13
for converting video and audio data into video signals and audio signals, an internal bus
11
for distributing video and audio data from the PCI bus
4
, and a control circuit
101
for reading video and audio data out of a main memory
2
and distributing them to the decoder
13
. The data input/output circuit
100
is also connected to the PCI bus
4
.
When video and audio data are to be outputted to the HDD
7
, the CPU
1
issues a command to the input/output circuit
100
to transfer the video and audio data to the memory
2
. The data input/output circuit
100
encodes the inputted video and audio signals by an encoder
103
, and transfers the generated video and audio data to the memory
2
via the PCI bus
4
. Further, the CPU
1
issues a command to the SCSIHA
6
to store the video and audio data stored in the memory
2
to the HDD
7
. The SCSIHA
6
, in compliance with the command, transfers the video and audio data stored in the memory
2
via the PCI bus
4
, and stores them in the HDD
7
.
When the video and audio data stored in the HDD
7
are to be outputted from the video output circuit
100
, the CPU
1
issues a command to the SCSIHA
6
to transfer desired data to the main memory
2
. The SCSIHA
6
, in compliance with the command so issued, reads the video and audio data out of the HDD
7
, and writes them into the main memory
2
. After that, the CPU
1
issues a command to the data output circuit
100
to transfer the video and audio data written into the main memory
2
to the decoder
13
. The control circuit
101
, in response to this command, reads the video and audio data out of the memory
2
in accordance with a frame reference signal inputted from outside, and outputs them to the decoder. The decoder, decoding the inputted video and audio data, and outputs them externally as video and audio signals. It externally outputs a plurality of uninterrupted video and audio signals, repeated frame by frame or in some other suitable units.
The method described above, whereby the same video and audio data are transferred via the same PCI bus
4
, involves the problem of low utilization efficiency of the PCI bus. That is, it was difficult to configure an image server for outputting a plurality of video and audio signals by using a plurality of data input/output circuits.
On the other hand, it is essential for an image server to secure. reliability against any HDD trouble. Known techniques against HDD trouble include RAID. According to RAID, a plurality of HDDs are used, and an SCSIHA generates a parity from data to be recorded in the HDDs, and records the parity in the HDDs
7
. When any HDD runs into trouble, the data recorded in the failed HDD are regenerated from the data and parity recorded in the remaining HDDs.
However, an SCSIHA having the conventional RAID function had only a small block for parity generation to adequately handle computer data. It is known that recording or reproducing with a small block relative to the HDD size results in a lower speed than recording or reproducing with a large block. In this context, the small block size refers to 512 bytes, which is the usual sector size of an HDD, and the large block size, generally 64 KB, 128 KB or more. Furthermore, an SCSII/F having a RAID function has a buffer memory for parity calculation and a CPU to control it, whose high cost poses another problem.
DISCLOSURE OF THE INVENTION
The present invention is intended to solve these problems with AV data input/output apparatuses according to the prior art.
According to a first aspect of the invention, there is provided an AV data input/output apparatus, having a second bus connected to a PCI bus, a memory connected to the second bus, and a decoder and an encoder connected by a buffer in-between, for storing AV data in an HDD. The AV data input/output apparatus according to the invention can increase the efficiency of PCI bus utilization and transfer AV data at a higher data rate by having an SCSIHA, when AV data are to be stored, directly read the AV data out of the memory and recording them into the HDDs and having the SCSIHA, when the AV data are to be outputted, directly write the AV data stored in the HDDs into the memory, so that the AV data need to be transferred via the PCI bus no more than once. Furthermore, the first aspect of the invention makes possible even more efficient transfers via the PCI bus by suspending, when it is to be accessed, data transfers from the memory to the decoder and data transfers from the encoder to the memory, and accessing the PCI bus.
According to a second aspect of the invention, a parity is calculated from the AV data outputted by the decoder in addition to the first aspect of the invention. The second aspect of the invention makes possible realization of a highly reliable AV data input/output circuit against HDD trouble by merely adding a parity calculating circuit and a data recalculating circuit. Furthermore, regarding the accessing of HDDs, it enables, as does in the first aspect of the invention, the maximum possible memory access to be accomplished, resulting in freedom from any drop in recording rate at the time of parity generation.


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