Auxiliary method for circuit design

Details Auxiliary method for circuit design Auxiliary method for circuit design

2006-11-29

2009-06-30

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07555737

ABSTRACT:
For accomplishing a circuit design, a first physical design is implemented according to a first netlist to obtain a first physical layout of a circuit. The first physical layout of the circuit is processed to obtain a first timing data. The first timing data is then inputted for timing verification of the first netlist. If the first netlist does not pass the verification, the first netlist is modified into a second netlist, while defining a modified portion of the netlist. Then, the modified portion of netlist is processed to obtain a second timing data, and the second timing data is used to overwrite a part of the first timing data. The first physical design is modified into a second physical design according to the second netlist only when the second netlist with the first timing data overwritten by the second timing data passes the timing verification, thereby improving time efficiency.

REFERENCES:
patent: 5508937 (1996-04-01), Abato et al.
patent: 6804810 (2004-10-01), Petersen et al.
patent: 2002/0023252 (2002-02-01), Lee et al.
patent: 2002/0078425 (2002-06-01), Mehrotra et al.
Edamatsu et al., Pre-layout delay calculation specification for CMOS ASIC libraries, Proceedings of the Asia and South Pacific Design Automation Conference 1998, Feb. 1998, pp. 241-248.

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