Auxiliary buffer for direct map cache

Details Auxiliary buffer for direct map cache Auxiliary buffer for direct map cache

1997-08-28

2001-07-03

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000

Reexamination Certificate

active

06256708

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a cache memory system for a computer system, and more particularly to a second level cache memory system having a second level cache memory which operates at a high speed and efficiently.
2. Description of the Related Art
An exemplary one of conventional second level cache memory systems is shown in FIG.
21
.
Referring to
FIG. 21
, the conventional second level cache memory system shown includes a central processing unit CPU
31
having a built-in first level cache memory (hereinafter referred to as L
1
cache memory)
32
, a second level cache memory (hereinafter referred to as L
2
cache memory)
33
of the direct map type, a main memory (main storage apparatus)
36
, a system controller
35
connected to control the main memory
38
, and a host bus
34
for interconnecting the CPU
31
, L
2
cache memory
33
and system controller
35
. A local bus master
38
is connected to the system controller
35
by a local bus
37
.
Since the L
1
cache memory
32
is built in the CPU
31
, it can process at a higher speed than the L
2
cache memory
33
. The L
2
cache memory
33
can process at a higher speed than the main memory
36
. The host bus
34
transfers an address, data, status and so forth,
In the conventional second level cache memory system having the construction described above, the L
2
cache memory
33
has a capacity larger than the L
1
cache memory
32
so that it stores part of data of the main memory
36
which are not stored in the L
1
cache memory
32
to improve the performance of the second level cache memory system.
In a cache system of the direct map type, communication of data between a main memory and a cache memory is performed in units of one line (block), and the main memory and the cache memory are physically divided and controlled in units of a line. Referring to
FIG. 22
) an address
41
of a line is divided into a tag (directory: address upper part)
42
and an index (address lower part)
43
. Since the cache system of the direct map type is a cache system of the one way set associative type and has a construction wherein tags and indices correspond in a one-by-one corresponding relationship, an address of a line to be stored into a cache memory is stored such that, based on the index thereof, a corresponding tag of the address is stored in a TAGRAM of the cache memory while data is stored into an address of a data storage memory of the cache memory corresponding to the index. Then, a tag of an address memory requested and tags stored In the TAGRAM of the cache memory are compared with each other, and when the tag of the memory requested address and a tag of the cache memory are equal and a VALID flag which represents whether or not the line of the address is valid indicates “valid”, the memory requested line results in cache hit. In any other case, the memory requested line results in cache miss.
Accordingly, in the conventional second level cache system of the direct map type, two lines having the same lower address, that is, the same index cannot be stored into the cache memory simultaneously.
On the other hand, in a second level cache system of the write back type (also called store in type), when a result of a memory write request is a second level cache hit, writing into the main memory is not performed, but only writing into the second level cache memory is performed. However, if a write miss of the second level cache memory occurs, the following two systems are available.
(1) Write allocate system: similarly as in a reading operation, even if a second level cache miss occurs, replacement of a line of the second level cache memory is executed.
(2) No write allocate system: when a result of a memory write request is a second level cache miss. replacement of the second level cache memory is not performed, but only writing into the main memory is executed.
A second level cache system of the write back type which is dealt with in the present specification presumes the no write allocate system when a result of a memory request is a second level cache miss. In a second level cache system of the write back type, when a result of a memory write request is a L
2
cache hit, since writing is performed only into the second level cache memory, data of the line stored in the second level cache memory is temporarily updated with respect to the main memory, resulting in temporary incoincidence of the data from data of the line stored in the main memory. Control is required to record it using a DIRTY flag that the data of the line stored in the second level cache memory has been updated with respect to the main memory to secure coherency of the data with the main memory. In the control, when replacement of the second level cache memory is performed because of a second level cache miss based on a result of a memory read request, if the VALID flag of the line delivered from the second level cache memory indicates “valid” and the DIRTY flag indicates “update”. the line is written back into the main memory once to assure coherency of the data. After the writing back, the read requested line is stored into the second level cache memory.
The conventional second level cache system of the direct map type additionally allows setting of a second level cacheable area, a non-cacheable area, a write-through area, a write back area and so forth in a relationship between the second level cache memory and the main memory. However, the conventional cache system of the direct map type has no measure for storing a particular memory area (hereinafter referred to as L
2
S cacheable area) as much as possible into the second level cache memory.
Also a method is available wherein a cache system of the two ore more way set associative type is improved in that, for example, one of the two ways is allocated and controlled as a way for exclusive use for the L
2
S cacheable area. However, where this method is employed, since the system construction is complicated and a higher cost than that of a cache system of the direct map type is required, it is difficult to improve the memory performance at a low cost. Accordingly, generally a second level cache system of the direct map type with which a memory system construction can be realized at a comparatively low cost is propagated widely as a second level cache system for a personal computer.
From the point of view of effective utilization of a L
2
cache memory, Japanese Patent Laid-Open Application No. Heisei 5-73415 discloses a countermeasure for reducing overlaps of lines stored in a first level (L
1
cache) cache memory in the inside of a CPU and a second level cache memory on the outside of the CPU. This countermeasure realizes effective utilization of the L
1
cache memory and the L
2
cache memory by employing means for exchanging, when a line corresponding to an address requested by the CPU is not present in the L
1
cache memory but present in the L
2
cache memory, a line present in the L
2
cache memory for another line present in the L
1
cache memory.
Meanwhile, Japanese Patent Laid-Open Application No. Heisei 5-257807 discloses a system which improves the processing speed in reading from a main memory when a L
1
cache read miss occurs and also a L
2
cache read miss occurs.
Further, Japanese Patent Laid-Open Application No. Heisei 4-288644 discloses a system wherein, when a read miss occurs both with a L
1
cache system and a L
2
cache system, not read data from a main memory are stored simply into the L
1
cache memory and the L
2
cache memory in an overlapping condition, but a first level cache monitor is adopted so that, depending upon the internal state of the L
1
cache memory, for example, in a case wherein an invalid (INVALID) cache line is not present in the L
1
cache memory, such processing that a cache line from the main memory is stored only into the L
2
cache memory but is not stored into the L
1
cache memory is performed in order to achieve effective utilization of the L
1
cache memory and the L
2
cache memory and redu

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