Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-09-24
1999-05-25
An, Meng-Ai T.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395580, 39580042, 711154, G06F 1300
Patent
active
059076933
ABSTRACT:
An electronic data processing circuit is disclosed having at least an instruction memory, an instruction decoder; and a slot structure. The slot structure is characterized by a plurality of slots. Each slot has at least: (1) an address register (2) a data register, (4) a function register, and (3) a monitoring circuit. Each slot asynchronously performs operations defined by the information content of their respective address register, data register and function register when complete information is present.
REFERENCES:
patent: 3715603 (1973-02-01), Lerch
patent: 4845633 (1989-07-01), Furtek
patent: 5121003 (1992-06-01), Williams
patent: 5382844 (1995-01-01), Knauer
patent: 5506998 (1996-04-01), Kato et al.
patent: 5673423 (1997-09-01), Hillis
David E. Muller, Asynchronous Logics and Application to Information Processing, Stanford University Press, Switching Theory in Space Technology, pp. 289-297, 1963.
Narinder Pal Singh, A Design Methodology For Self-Timed Systems, Massachusetts Institute of Technology, MIT/LCS/TR-258, Feb. 1981.
T. S. Anatharaman, A Delay Insensitive Regular Expression Recognizer, Dept. of Computer Science, Carnegie-Mellon University, CMU-CS-89-109, Jan. 1989.
Jens Sparso, et al., Design of Delay Insensitive Circuits Using Multi-Ring Structures, European Design Automation Conference, IEEE 0-8186-2780, pp. 15-20, Aug. 1992.
Lawrence G. Heller, et al., Cascode Voltage Switch Logic: A Different CMOS Logic Family, ISSCC 84 Digest of Technical Papers, IEEE, pp. 16-17, Feb. 1984.
Wojcik et al., On the Design of Three Valued Asynchronous Modules, IEEE Transaction on Computers, Oct. 1980, vol. C-29, No. 10, pp. 889-898.
Shibata et al., A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, IEEE Transactions On Electron Devices, Dec. 1992, vol. 39, No. 6, pp. 1444-1445.
Mark Edward Dean, Strip: A Self-Time Risc Processor, Jun. 1992.
M.R. Greenstreet, T.E. Williams, and J. Staunstrup, Self-Timed Iteration, Elsevier Science Publishers B.V. (North-Holland), IFIP, 1988, pp.309-322.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt, Automatic Synthesis of Asynchronous Circuits from High-Level Specifications, IEEE Transactions on Computer-Aided Design, vol. 8, No. 11, Nov. 1989, pp. 1185-1205.
Ted Williams, Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
Jens Sparso and Jorgen Staunstrup, Delay-insensitive multi-ring structures, INTEGRATION, the VLSI Journal 15, 1993, Elsevier Science Publishers B.V., pp. 313-340.
Tzyh-Yung Wuu and Sarma B.K. Vrudhula, A Design of a Fast and Area Efficient Multi-Input Muller C-element, IEEE Transactions on VLSI Systems, vol. 1, No. 2, Jun. 1993, pp. 215-219.
Marc Renaudin and Bachar El Hassan, The Design of Fast Asynchronous Adder Structures and Their Implementation Using D.C.V.S. Logic, Int'l. Symposium on Circuits & Systems, vol. 4, 1994, pp. 291-294.
Richard G. Burford, Xingcha Fan and Neil W. Bergmann, An 180 Mhz 16 bit Multiplier Using Asynchronous Logic Design Techniques, IEEE 1994 Custom Integrated Circuits Conference, pp. 215-218.
Ted Williams, Self-Timed Rings and Their Application to Division, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
Stephen H. Unger, Asynchronous Sequential Switching Circuits, 1969, pp. 221-229.
Carver Mead & Lynn Conway, Introduction to VLSI Systems, 1980, pp. 242-262.
Ivan E. Sutherland, Micropipelines, Communications of the ACM, Dec. 1989, vol. 32, No. 6.
Hampel et al., Threshold Logic, IEEE Spectrum, May 1971, pp. 32-39.
Brzozowski et al,. Asynchronous Circuits--Monographs in Computer Science, Springer-Verlag New York, Inc., 1995, New York, NY.
Fant Karl
Kinney Larry
An Meng-Ai T.
Ciccozzi John
Theseus Logic Inc.
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