Autonomous way specific tag update

Details Autonomous way specific tag update Autonomous way specific tag update

1999-09-02

2002-06-18

Lane, Jack A. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000, C711S156000

Reexamination Certificate

active

06408361

ABSTRACT:

FIELD OF THE INVENTION
The disclosed invention relates to autonomous, way specific tag updates. Autonomous, way specific tag updates are achieved by allowing a concurrent read of non-utilized ways during the specific update of a single way.
BACKGROUND
As technology in the computer industry advances, the speed of which information is processed and accessed is increased. One advance is the use of a cache system. The cache system includes a cache controller and a cache memory. Levels of cache memory differ according to their proximity to the processor. For instance, a cache memory resident on the chip with the processor is generally referred to as a level 1 (L1) or level 2 (L2) cache. A cache memory that is resident off of the processor chip is typically referred to as a level 3 (L3) cache, however, the cache directory portion of the L3 cache memory may reside on the microprocessor chip. The cache memories typically store a subset of what is stored in larger main memory. However, the access speeds for the small cache memories are very high, thus allowing a very short access time.
A cache memory stores frequently accessed main memory data. Thus, the processor accesses the faster speed cache memory to retrieve information without accessing the slower main memory. The most frequently addressed data is held in the cache memory. The cache controller intercepts memory requests then determines if the cache memory contains the data that was requested by the processor. If that information is stored in the cache memory, then the request is redirected from main memory to the cache memory. Because of the small size of the cache memory, the cache memory must be continuously updated with recently requested information. In a typical transaction, the main memory address is compared with the stored addresses in the cache directory of the cache memory to determine if the data resident at that address is stored in the cache memory. If that information is stored in the cache memory, then the information is sent from the cache memory at a relatively fast rate. However, if the information is not resident in the cache memory, then the information is obtained and delivered to the processor from main memory. The information coming back from main memory is also stored in the cache memory as this data was recently requested. While this information is being written to the cache memory, the cache memory cannot be read to determine if the next memory address request is resident in the cache memory. Even the faster access cache memories are limited to serial read and write transactions so that they can maintain data coherence.
Information stored in the cache memory may also contain a status. The status of the cache memory entry can be identified by the MESI Protocol (modified, exclusive, shared, invalid). Thus, certain transactions may not modify the data stored in the cache memory, but they may change or modify the status of that specific cache memory entry. While a status is being modified or updated, no reads can be performed; thus, status updates are serial.
Therefore, any advancement in the ability to increase the number of reads and writes to cache memory during a given clock period would be beneficial.
THE SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for allowing autonomous, way specific tag status updates. More specifically, the invention provides way specific tag updates while concurrently allowing reads of the ways not currently being updated. If a read hit is determined, then the read is processed in a typical fashion. However, if a read miss is determined and a way update is flagged, then all ways are read after the specific way has been updated.


REFERENCES:
patent: 5802586 (1998-09-01), Jones et al.
Messmer, Hans-Peter.The Indispensable P.C. Hardware Book: Your Hardware Questions Answered. (Second Edition) Addison-Wesley. New York, 1995, pp. 211-226.
Kozierok, Charles M. “Function and Operation of the System Cache,”P.C. Guide. http://www.pcguide.com/ref/mbsys/cache/func-c.html, Dec. 16, 1998 vers., pp. 1-3.
Kozierok, Charles M. “Layers of Cache,”P.C. Guide. http://www.pcguide.com/ref/mbsys/cache/layers-c.html, Dec. 16, 1998 vers., pp. 1-3.

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