Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-05-24
2005-05-24
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S022000, C710S023000, C710S024000, C710S025000, C710S026000, C710S027000, C710S028000, C712S011000, C712S012000, C712S033000, C712S034000, C712S035000
Reexamination Certificate
active
06898657
ABSTRACT:
A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. Configurable signal processing logic may be configured to host one or more signal processing functions which allow data to be autonomously accessed from the processor local memories, processed, and re-deposited in a local memory.
REFERENCES:
patent: 5197130 (1993-03-01), Chen et al.
patent: 5784630 (1998-07-01), Saito et al.
patent: 6167502 (2000-12-01), Pechanek et al.
Chen Alan S.
Frantz Robert H.
Gaffin Jeffrey
Tera Force Technology Corp.
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