Automatic wiring method for the crosstalk reduction

Details Automatic wiring method for the crosstalk reduction Automatic wiring method for the crosstalk reduction

2008-01-29

2008-01-29

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S002000

Reexamination Certificate

active

10888635

ABSTRACT:
A computer implemented method for designing a semiconductor integrated circuit includes extracting a global wire susceptible to an influence of crosstalk from among a plurality of global wires passing through a switchbox including a plurality of global routing grids based on a crosstalk standard; setting up a crosspoint restriction to restrict a crosspoint of the global wire susceptible to the influence of the crosstalk intersects with a boundary of the switchbox, based on a wiring restriction data; and carrying out detail wiring of the switchbox based on the crosspoint restriction.

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patent: 2005/0251775 (2005-11-01), Wood
patent: P2000-223578 (2000-11-01), None
patent: P2002-222865 (2002-09-01), None
patent: 2002-328963 (2002-11-01), None
Tseng et al., “Timing- and crosstalk-driven area routing”, Apr. 2001, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 20, Issue 4, pp. 528-544.
H.P. Tseng et al, “Timing and Crosstalk Driven Area Routing,” DAC98—35th Design Automation Conference, Jun. 15-19, 1998, San Francisco, CA.
Official Office Action Letter issued Oct. 2, 2007 in counterpart Japanese application (Application No. 2003-371785), with English language translation.

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