Automatic wiring method and apparatus for semiconductor...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07496878

ABSTRACT:
A semiconductor package automatic wiring apparatus which determines an optimum wiring route from each pad to a corresponding one of vias on a semiconductor package having a multi-tier bonding pad structure in which pads to be connected to a semiconductor chip are arranged in multiple rows, comprises: row identifying means for identifying each pad as to which row the pad belongs to; tentative placement means for mapping the position of the pad to a position on a matrix table after the pad has been identified by the row identifying means as to which row the pad belongs to; and determining means for determining the optimum wiring route based on the matrix table generated by the tentative placement means.

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patent: 2000-35986 (2000-02-01), None
patent: 2001-15637 (2001-01-01), None
patent: 2002-83006 (2002-03-01), None

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