Automatic topology synthesis and optimization

Details Automatic topology synthesis and optimization Automatic topology synthesis and optimization

1998-10-01

2001-04-24

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06223334

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to the field of Electronic Design Automation (EDA). More particularly, this invention relates to a method and apparatus for automatic topology synthesis and optimization.
BACKGROUND OF THE INVENTION
Advances in chip manufacturing technology have lead to printed circuit boards with input/output drivers having very fast signal transition times. Fast signal transition times can make even short interconnects behave like transmission lines with all of the related signal integrity problems. Clock frequencies in system designs have also continued to increase. Faster clock frequencies result in tighter delay margins when designing interconnects. Thus, the challenge of today's high speed board design is to design the interconnects within the available delay margins while maintaining the desired signal quality. Signal quality is usually measured in terms of overshoot, undershoot, monotonicity, and ringback.
The above mentioned interconnect design problem is critical for high speed nets with a large number of pins. It is even more critical for nets with bi-directional drivers, since it is necessary to make sure that the timing margins and signal quality are maintained for every driver on the net.
Designing interconnects to meet the specified constraints consists of two stages. One stage is topology design and the other stage is termination selection. For example, a daisy chain topology may be designed having a series termination scheme. In today's design methodology, both stages are frequently done manually. For instance, a designer may manually explore the infinite space of possible topologies and termination schemes for each net in a design. This is a very time consuming task where the engineer has to set up simulations for each design point to verify the delay and signal quality constraints are met.
A need exists, therefore, for a design tool which can automate topology and termination selection for a general net, while adhering to delay and signal quality constraints. In particular, an automated design tool is needed for interconnecting multiple pin nets and nets with bi-directional drivers.
SUMMARY OF THE INVENTION
The present invention includes a net topology strategy, referred to as a J-tree model, that meets monotonicity and ring back constraints for nets with bi-directional drivers without much degradation in delay. The present invention includes a method that can be used to automatically construct a J-tree for a given net. A J-tree is generated by identifying at least two clusters of nodes and interconnecting the nodes so that each node has a sibling node that is the same distance from a parent node. Each cluster comprises at least a minimum geometric number of nodes. The nodes are interconnected by first locating a star point for each cluster so that the nodes in each cluster are equidistant from the star point. Then, the star point for each cluster is interconnected forming the topology.


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Place and Route: and Man vs. Machine;Authors: Rod Strange and Peter Suaris; Miller Freeman, Inc. reprinted with permission from Printed Circuit Design, The Definitive Journal of Printed Circuit Board Design, Dec. 1995, vol. 12, No. 12, no page #.

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